Research On Single Event Effect Test Method Of High Speed Serial Interface

High speed serial interface(Ser Des)chips are widely used in the fields of high bandwidth applications such as radar,radio communication image imaging in aerospace engineering and weapon equipment.It has gradually become the standard interface for data transmission of ultra-high speed converters.Single event effect is the main factor that affects the normal operation of high-speed serial interface chip in space.Due to the characteristics of high-speed serial interface chip,such as high speed,various functions and complex structure,the single event performance evaluation of high-speed serial interface chip is greatly challenged.In order to comprehensively and clearly analyze the single event effect of high-speed serial interface chip,this paper gives the type of single event effect of this chip and its detection method by studying the structure,functional characteristics and protocol standards of typical high-speed serial interface chip JESD204 B.Combined with the characteristics of single event effect of high-speed serial interface chip,the calculation method of bit error rate caused by single event of high-speed serial interface is presented.In order to solve the problem of high speed serial interface chip single event effect test speed and difficulty for data detection.Based on the research of high speed serial interface chip single event test at home and abroad,a parallel terminal detection method using parallel series-parallel data transmission mode is proposed.The function and division of each module of FPGA were improved,the single event test board was redesigned,and the testing system was tested and verified.The JESD204 B high speed serial interface receiver chip was subjected to heavy ion tests to evaluate the cross sections,thresholds,on-orbit soft error rate and bit error rate caused by single event effect of the chip.The sensitive module of JESD204 B high speed serial interface receiver chip is analyzed by means of pulse laser test,which locates the specific sensitive unit of the device and combines the phenomena of heavy ion and pulse laser test.The aim is to provide some help for the design of high speed serial interface chip for radiation resistance reinforcement and the test method guidance for radiation resistance evaluation.