Design And Implementation Of FPGA-based Network Message Analysis And Performance Test Unit

With the rapid development of the Internet,network infrastructure equipment has been widely used,and a large number of network performance testing requirements have emerged.Therefore,the development of a network tester with high cost performance,high reliability,high precision,and network performance test function,has important engineering application value.The dissertation mainly completed the design and implementation of network message parsing and performance testing unit based on Field Programmable Gate Array(FPGA).Firstly,the paper introduces the network protocol,test protocol and test theory related to the network tester system,and gives the overall structure of the network tester system.Then,according to the functional requirements of the network tester system,the FPGA scheme for implementing the network packet parsing and performance test unit is given,and each module in the FPGA scheme is designed and simulated.Finally,the network packet parsing and performance testing unit is fully debugged in the entire network tester system platform,and the basic functions of the network packet parsing and performance testing unit are verified.Through debugging and verification,the network packet parsing and performance testing unit designed by the paper supports the parsing and processing of various common network packets,and realizes the delay test and the ring network self-healing test function,which can provide a reliable network performance test method.