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Design Of A Multifunction Network Tester And The FPGA Implementation Of Its Packet Processing Module

Posted on:2012-08-06Degree:MasterType:Thesis
Country:ChinaCandidate:H MaFull Text:PDF
GTID:2248330332988125Subject:Communication and Information System
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With the rapid development of broadband network equipments, the domestic demand for the test instruments of these network equipments is becoming larger. A variety of network test instruments have been developed abroad, but they are quite expensive and inconvenient for use. The domestic test instruments are so simple in function and inferior in performance that they can not meet the domestic test requirements of network equipments. Therefore, the detailed research of the multifunction network tester, including its hardware design scheme and the FPGA implementations of its core modules, such as GE payload processing module and HDLC packet processing module, is of great application sense for developing network testers with high performance/cost ratio.This dissertation firstly introduces the present research status and background of the network testers both at home and abroad, as well as the research significance. Secondly, it gives a description of basic working principles of the SDH technology, HDLC protocol and GE, and provides a comparative analysis on the performances of the existing network testers. Then the overall implementation scheme of the hardware platform of a multifunction network tester to be addressed is designed with a detailed discussion on the hardware design of chips for the SDH, AAL5 and test data processor. On this basis, the overall scheme of the core component of a multifunction network tester, test data processor, is presented. The study emphasis is put on the functions and implementation schemes of the GE payload processing module and HDLC packet processing module. With the help of the Altera Stratix II FPGA, this dissertation implements the functions of all sub-modules of the HDLC packet processing module with VHDL programming and completes the overall simulations and verifications, which show that all the implemented sub-modules have fully met the design requirements of the tester. Finally, the summary of the whole dissertation is given and the issues to be studied further are proposed.
Keywords/Search Tags:Network Tester, Synchronous Digital Hierarchy (SDH), High-level Data Link Control (HDLC), Gigabit Ethernet (GE), Field Programmable Gate Array (FPGA)
PDF Full Text Request
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