Design And Implementation Of Gigabit Ethernet Test System Based On FPGA

Nowadays,communications are developing more and more rapidly.Network has become a necessary part of people's life.Gigabit Ethernet,the main force of LAN,plays a vital role in the network.The performance of network device will influence the stability and reliability of the network.So the performance of the network device has to tested that can maintain the network device.Therefore,this paper aim to design a test system which can test the performance of network devices in Gigabit Ethernet transmission network based on RFC2544 standard.In this paper,the performance test system of network device in Gi gabit Ethernet is studied and designed.First of all,this paper deeply analyzes the basic theory of Gigabit Ethernet,and designs an Ethernet test frame structure.Secondly,the indexes of RFC2544 test standard and the testing methods of each performance index are studied and analyzed in depth.Through the analysis of each performance index of RFC2544,a design scheme of network performance testing system for equipment of Gigabit Ethernet is put forward.Thirdly,the hardware of the system is selected according to the requirements of the design scheme.And the Xilinx company's Spartan6 series FPGA development board is used for the platform to design the system's sending module,packet making module,sending control module,receiving module,and receiving processing module.The design is implemented by Verilog HDL language,and the function of the test system is simulated by Modelsim software.Finally,the system is debugged by Chipscope.And the control interface of PC is connected with USB Uart interface.And the test results are displayed on PC.The system is used to test the related performance of the network device.The test results show that the system can meet the design requirements.And it has a certain theoretical and practicality.