Configurable NAND Flash Error Correction Technology Research

In recent years,the semiconductor solid-state memory represented by NAND Flash has become the main choice of external memory in various types of electronic products with the rapid development of large-scale integrated circuit technology,and which is widely used in embedded and mobile devices because of its large capacity,high storage density,high access speed,low cost and low power consumption.As the storage capacity constantly goes up and process size continually decreases,the reliability and service life of the memory are facing serious challenges due to charge leakage,program disturb,read disturb,retention time,increase in program/erase cycle,etc.In view of this situation,a mode configurable ECC error correction system circuit structure based on BCH code is completed.This structure has implemented the BCH encoding and decoding circuits of(8640,8192,32),(8416,8192,16),(8304,8192,8),and the error correction mode can be configured according to the memory error rate,power consumption is reduced by rationally configuring internal circuit resources.Based on the traditional design,each module of the BCH code has been effectively optimized: 1)The encoder adopts a mode-configurable 8-bit parallel coding design,and the encoding circuit with stronger error correction capability can multiplex the encoding circuit with weaker error correction capability;2)The syndrome calculation module calculates the remainder and employ 8-bit parallel design,which reduce the resource consumption of the Finite Field Multiplier and Finite Field Adder to 26/(n-1)for solving a syndrome.And the resource consumption of the entire syndrome calculation module has been reduced by about50%;3)Compared with the traditional BM iterative algorithm,the error position polynomial using SiBM iterative algorithm reduces the number of iterations by half,avoids the calculation of inversion and saves a large amount of circuit area;4)The hardware consumption has been greatly reduced by applying the parallel Chien search algorithm of the constant Finite Field multiplier(CFFM)in the error mode calculation.Compared with the single mode of BCH code(8640,8192,32),the proposed design significantly reduces the power consumption in the case of low BER decoder,which only sacrifices a few hardware resources consumption.In the three modes,the number of errors is 8 bits,and the power consumption of each module of the decoder is mainly analyzed.The result is as follows: The optimized BCH decoder of errorcorrection capability of t=8,particularly,the syndrome structure,SiBM algorithm structure,Chien search structure save power consumption of 49.7%,0% and 64.9%.Error correction capability of t=16 BCH decoder,syndrome structure,SiBM algorithm structure,Chien search structure are of 34.7%,0% and 42.4% power saving.And for the BCH decoder of t=32,the power saving are 1.1%,0% and 0%respectively.The error correction system is based on Xilinx Zynq series xc7z020c1g484 chip and the circuit simulation and synthesis is done by Xilinx Vivado.