Research Of BCH Encoding And Decoding Technology Based On NAND Flash

With the rapid development of information technology, the traditional SLC(Single-Level Cell) architecture of NAND Flash has hardly satisfy the requirements ofhigh-capacity and low-cost memory, and With the advantage of lower cost per bit andhigher storage density, MLC (Multi-Level Cell) architecture of NAND Flash is widely usedin a variety of storage systems among. However, due to the increase of internal voltage level,MLC NAND Flash has higher probability of bit error in the erase and write process, thetraditional single-bit error correction code-Hamming which has been unable to meet thedemand of error correction.BCH code is more suitable for more bits error correction ofNAND Flash because of its simple structure, something easy to achieve, stronger errorcorrection capability, Shorter checksum and so on, therefore the article will conducted theresearch of BCH codec technology on NAND Flash.According to the internal structure characteristics of NAND Flash, designed the errorcorrection capability for each512bytes can correct8bits of BCH code. Firstly, the articlestart to unfold on theoretical basis code and construction method of BCH code step bystep,Solution process of generator polynomial is more complex and error-prone when BCHcode has longer information symbol,to solve this problem by using Matlab to replacelook-up table method to improve efficiency.Choosing8bits parallel BCH encoding as ahardware implementation method of the BCH encoder, which solves the problem of theserial BCH encoder encodes slow and digits do not match with the NAND Flash, but alsoreducing high fan-out circuits bottleneck of the encoder linear feedback shift register.BCHdecoder as a whole is the most complex in the design of algorithm, and is also taking up themost part of the logic resources, In this paper,Using a variety of optimization designmethods in the its design process. In measures of improve decoding rate,it saves8times time to adopt the method ofparallel processing in the the syndrome calculation module and the chien searchmodule;besides,the method of secondary flow line structure of block decoding whichgreatly reduces decoding time in one page of data to improve the efficiency of decoding.And the simplified without inversion algorithm is used in the solving process of errorlocation polynomial, compared with the traditional inverse algorithm circuit structure issimple, but also the algorithm greatly reduces the footprint of logical resource, savehardware cost. Finally, we build simulation platform to simulate for BCH codec, simulationresults show that the function of the BCH codec has reached the expected requirement.