The Research On NAND Flash Coding For Low-power And Low-BER In The SSD

With the rapid development of information technology,solid-state storage system's highly performance,small size,no noise and etc make it is widely used.However,with the continuous improvement of the production process of solid-state storage devices,solid state drive(SSD)in the data error rate is increasing,it is essential to precode to the data stored in solid state drive.In this paper,the data in NAND flash memory due to its physical causes of data retention errors and program disturbance errors,in order to reduce power consumption and improve the reliability of the data,we focusing on NAND flash coding for low-power and low-BER.Include the following aspects:1.First,this paper presents a low-power and low-BER flash coding scheme called Write Pattern Format Algorithm(WPFA algorithm),All-flipping or half-flipping the initial data according to the most significant bit(MSB).Thus,the Algorithm can eliminate the CSPs data pattern,reducing memory power consumption and improve the reliability of data.2.then,we proposed a low-power and low-BER flash coding scheme called a iterative algorithm(XOR algorithm),makes the data iterative XOR with the adjacent data,After XOR algorithm optimized data can not only reduce CSPs data mode,reducing power consumption of flash memory,and can reduce the data error rate and improve data reliability,but also simplifies the logic circuits.3.Finally,comparison of the WPFA algorithm and iterative XOR algorithm based on power,space overhead and reliability.The results shows that the WPFA algorithm can effectively eliminate CSPs data patterns to improve the reliability of the data,but the XOR algorithm compared to WPFA algorithms perform better in terms of power consumption and fault tolerance.