ASIC Design Of High Performance FFT In OFDM System

With the advent of the 5G era,human communication needs have lower latency and more scenarios.5G new infrastructure is the new wind of China's future economic construction.5G communication speed is faster and faster,and the transmission bandwidth is wider and wider.At present,there are many problems to be solved in the development of all kinds of communication technologies.The latest 5G NR(new radio)and ieee 802.11ax protocols,their core technology is OFDM(Orthogonal Frequency Division Multiplexing),which uses multiple spectrum overlapping and Orthogonal subcarriers for information transmission,compared with the traditional modulation method in the system spectrum utilization is improved.FFT processor is the core of OFDM,and its result is directly related to OFDM performance.However,in the 5G era,FFT processor with large number of points in OFDM system has new requirements,such as low delay and high signal-to-noise ratio.At present,the large number of FFT processors in OFDM system has the low performance of high delay and low signal-to-noise ratio,which cannot meet the requirements of 5G era.Therefore,the research of high performance FFT processor with large number of points,low delay and high signal-to-noise ratio is of great significance to the design and optimization of OFDM system.This paper first introduces the basic principle and classic architecture of OFDM system,simulates the transmitting and receiving parts of OFDM by MATLAB software,analyzes the requirements of FFT in OFDM,and conducts fixed-point simulation of FFT.A kind of high performance FFT ASIC(Application Specific Integrated Circuit)in OFDM system is designed,which can complete the fixed-point FFT operation at4096 points.The implementation of FFT circuit is divided into six sub-modules:counting control module,state control module,address generation module,butterfly computing module,rotation factor addressing module and improved variable bit width module.In the design,the traditional recursive architecture is firstly improved,and seven roms are used to store the rotation factor,so that the butterfly operation is completed in one cycle,so that the butterfly operation is no longer vacant.On complete base 8 operation,the overall cut a method of adaptive variable width unit design,it is a combination of low and high saturation algorithm,after using the adaptive cut a whole design signal-to-noise ratio of 46.3112 d B,relative to the interception of low and high saturation algorithm to get higher SNR,dual port RAM logical resource saving of42.9%.The function simulation of submodule is completed.By comparing the result of fixed point C's FFT function with the result output of this FFT processor,the RTL function simulation is tested and its correctness is verified.In order to prove the design of high performance indicators,low delay and high signal-to-noise ratio.Compared with the general recursive architecture and relevant literature,the delay of 2096 cycles of functional simulation is relatively better,and the low delay is verified.The running time is 102.88?s on a 100MHz FPGA.By comparing the RTL test results with MATLAB floating point function FFT,the SNR is 53.98d B in the case of a single sinusoidal wave with noise at 15MHz frequency and 150MHz sampling rate.In the case of 1200 amplitude broadband signal,the SNR is 44.68d B,and the performance is better,which verifies the high SNR.Logic synthesis and Static Timing Analysis(STA,Static Timing Analysis)were carried out by the Design Compiler of synopsys.Finally,the area was 0.46mm~2 and the power consumption was 95.03mw,which met the requirements of STA and verified the low area and feasibility.Experimental results show that the high performance FFT processor in OFDM system designed in this paper meets the requirements of high performance FFT processor in OFDM system in terms of delay and signal-to-noise ratio.The high performance FFT ASIC design of OFDM system proposed in this paper is of great significance for further research on FFT processor.