Research And Design Of OFDM Baseband Chip Synchronization Technology

Orthogonal Frequency Division Multiplexing not only has high spectral efficiency,but also has a good effect to against the frequency selective fading, so it has been widely used in wireless communication systems. However, as a multi-carrier modulation technique, OFDM is very sensitive to synchronization error, and therefore synchronization plays a crucial role in the baseband design.In this paper, OFDM system synchronization is in-depth study, summarizes the three major issues that will be resolved by synchronization:(1). Because the receiver does not know the start position of a frame, the frame data can not be made FFT transform correctly;(2). Since the data is transmitted in the wireless channel, the received carrier waves have frequency deviation, resulting in non-orthogonal between subcarriers;(3).Because the receiver and the transmitter sampling clock is independent, there is a certain sampling frequency deviation in the frame data. According to these three questions, This article made improvements in three areas:(1) improved symbol timing synchronization algorithm, so that the symbol timing is not only compatible IEEE 802.11 a, and can be compatible protocol which has similar physical frame format;(2) increased integer multiples of the carrier synchronization, in order to increase the carrier frequency biased estimation and compensation range, the normalized compensation range is [4,4].The front part of the circuit design, this paper gives the structure of each synchronization module hardware implementation, and simplification of complex algorithms, and proposed a hardware circuit design optimization, For example complex multiplier, CORDIC frequency offset estimation and compensation, delay and other inter-related operations. Then, completed and passed the RTL simulation of synchronization module. The end part of the circuit design, each synchronization module is designed with SMIC 0.13?m CMOS technology, and IP cores of SRAM instead of registers which are used for data storage and delay,in order to reduce the power and area of chip design. Then, completed and passed the layout design and back-end simulation of synchronization module. Time-domain synchronous layout area is 1.88mm2, power is9.5m W, the highest clock cycle is 15 ns. Integer carrier synchronization layout area is0.65mm2, power consumption is 3.77 m W, the highest clock cycle is 12 ns.Frequency-domain synchronous Layout area is 0.59mm2, power is 1.9m W, the highest clock cycle is 10 ns.