Research And Implementation Of HARQ Transmission Mechanism In 5G

With the rapid development of information industry and the popularization of the new services such as live show and virtual reality,the fifth generation of mobile communications system(5G)has proposed higher requirements from the aspects of transmission rate,bandwidth and delay.HARQ is a key technology which is through physical layer(PHY)and MAC to achieve the purpose of low delay in 5G.It makes use of the error correction ability of the channel coding,and retransmits the code which is wrong in the first transmission to increase the information of decoding bits.We study and research the 5G HARQ retransmission scheme first,and then complete the hardware architecture design and FPGA implementation of some part of receiver.The main work is as follows:(1)Based on the 5G NR standard,we built the 5G link-level simulation platform which supports HARQ,complete the part including transmitter,physical channel and receiver.We give a key research of the new technology in PHY such as the encoding and decoding of QC-LDPC,the design of HARQ architecture in both transmitter and receiver.Based on the platform,we analyze the gain of retransmission under different channel environment and give a simulation of the new proposal in 5G which the retransmission unit is Code Block Group(GBG).(2)We propose a new adaptive HARQ retransmission scheme for 5G data channel.We divide several sub-channels of the equivalent channel which the code blocks pass,and remaps the starting position of the retransmission through the sub-channel quality fed back by the receiver.In that case,the data retransmitted are maped onto the sub-channels that have better channel quality to achive higher diversity gain in next retransmission.The performance of new scheme is analyzed based on the link-level platform,and the results show that compared with the 5G NR standard,the new scheme can obtain a gain of about 0.45 to 0.5dB.(3)Finally we give the hardware implementation of receiver HARQ retransmission and the DDR arbitrator control.To prevent the simultaneous occurrence of reading and writing requests,we design the DDR arbitrator control machine with FPGA,which complete the function of parsing PDU header,which includes the write and read control module,DDR arbitrator module and the DDR IP Core.And we also implement the round robin arbitrator algorithm with FPGA.The throughput of HARQ module we designed can achieve of 10.6Gpbs to meet the requirements of 5G.