FPGA Design And Implementation Of Unstructured LDPC Code

Low density parity check(LDPC) code has a good decoding performance, and its decoding complexity is low. The FPGA implementation of LDPC codes has been seriously adopted in digital television and deep-space communications. Compared with structured LDPC, non-structured LDPC has a better decoding performance because of its randomness, but its check matrix has not cyclic structure or quasi-cyclic structure, which increases the difficulty of the decoder design, and its irregular degree distribution increases the complexity of the FPGA implementation. Therefore the paper focuses on the design of unstructured LDPC decoder, and introduces a particular mapping based on the permutation of its check matrix, which can greatly minimize the impact of the irregular degree distribution. The paper does the following works in different aspects.The paper compares structured LDPC and non-structured LDPC, which also describes the Sum-Product algorithm, Min Sum algorithm, and Normallized Min Sum algorithm in detail, which analyzes the advantages and disadvantages of the algorithms. The performance results are computed using different algorithms.The paper specifically compares the advantages and disadvantages of FPGA implementation using structured LDPC and non-structured LDPC, which also introduces a method to simplify FPGA implementation of non-structured LDPC and greatly reduce the hardware implementation complexity of the decoder. The paper analyzes the quantization scheme and some key parameters of the decoding algorithm.According to the method reducing FPGA implementation complexity of non-structured LDPC, the paper designs a LDPC decoder with serial structure, and complete logic synthesis and timing simulation, which verifies the correctness of the LDPC decoder. For the FPGA design and implementation of non-structured LDPC decoder, the paper introduces a way to improve the decoder’s working frequency by achieving the parallel decoding.It turns out that the design of unstructured LDPC can normally operation, which achieves the maximum operation frequency of 213.549 MHz and reaches data throughput of 20 Mbps.