Simulation And Mapping Method Of 2d Grid Coarse Grained Reconfigurable Computing Component Control

In recent years,two-dimensional grid-type coarse-grained reconfigurable computing systems have attracted the attention of scholars in the field of computing control because of their significantly higher computational efficiency than other integrated systems,and has been widely applied in configuration computing,computer control,image acceleration and other fields.In this paper,the logic design and simulation of 2d grid coarse-grained reconfigurable computing component control are carried out,the dynamic and static power consumption of the total adder and other computational control components is analyzed comprehensively,and the mapping method of the grid reconfigurable cell array is studied from the compilation level.Its main work and innovations are described as follows:(1)This paper studies the framework of grid coarse-grained reconfigurable computing system,understands the interconnection mode of components and configuration operation mechanism of grid coarse-grained reconfigurable computing system,and proposes a quantitative evaluation method of grid coarse-grained reconfigurable computing system.(2)This paper studies the design verification method of computing module of two-dimensional grid coarse-grained reconfigurable system,The full adder and multiplier of coarse-grained reconfigurable computing system have been comprehensive designed and verified,Design language is Verilog HDL.The dynamic power,junction temperature and the use of hardware resources for the multiplier of two bits,four bits,eight bits,sixteen bits,thirty-two bits and the full adder of two bits,four bits,eight bits,sixteen bits,thirty-two bits have been analyzed and compared.The multiplier schematic diagram and the test code are designed.Compare with two bits full adder,the experimental results show that the dynamic power,junction temperature,look up table and I/O of thirty-two bits full adder have increased by 20.519w,38.9?,28 and 90.Compared with the two bits multiplier,the dynamic power,junction temperature,look up table and I/O of thirty-two bits full adder have increased by 0.603w,1.1?,28 and 114.With the increase of the number of bits,the dynamic power,junction temperature,look up table and the number of I/O of the full-adder have higher consumption.However,the dynamic power,junction temperature of the multiplier have lower consumption.Look up table and the number of I/O have higher consumption.(3)The method of grid reconfigurable cell array mapping is studied.Aiming at the mapping problem of grid-type coarse-grained reconfigurable cell arrays,two mapping methods,row extraction and column extraction,are proposed.The goal of the row extraction mapping algorithm is to obtain a smaller execution delay of the computing task;the goal of the column extraction mapping algorithm is to obtain a smaller communication between reconfigurable computing array blocks.The program-transformed DFG graph is mapped into a coarse-grained reconfigurable system with a variety of mapping rules.The experimental results show that:Compared with the traditional SPKM(Split-Push Kernel Mapping)algorithm,the row extraction algorithm reduces the number of refresh blocks M by 46.4%(PEA4*4),50.6%(PEA4*5),and 48.4%(PEA5*5);The computing delay Ssd was reduced by 90.3%(PEA4*4),91.0%(PEA4*5)and 92.6%(PEA5*5)on average.The column extraction algorithm reduced the average number of refresh blocks M by 51.0%(PEA4*4),61.0%(PEA4*5),and 59.3%(PEA5*5);the average operation delay Ssd was reduced by 72.2%(PEA4*4),77.3%(PEA4*5)and 80.0%(PEA5*5).But both have increased in non-primitive input and output.