Design Of High-Precision Time-to-Digital Converter

Time interval measurement technology has been increasingly used in engineering fields such as laser ranging,3D imaging and geological exploration.It is also widely used in academic research such as nuclear physics and biomedicine.Time to Digital Converter(TDC)is a circuit system dedicated to time interval measurement.In recent years,the precise measurement requirements of time intervals in various engineering and scientific research fields have led to the rapid development of TDC research.Aiming at the high-precision design index requirements,the theoretical models of various single-mode TDCs are studied and analyzed.The accuracy of state-sampling TDC is quantitatively analyzed,and the performance of several high-precision fine-resolution TDCs are analyzed and compared.Based on this,a three-stage TDC circuit based on two-stage DLL is designed.The high section uses the counter type TDC to extend the range,the middle section uses the multiphase clock interpolation type TDC based on state sampling,and the low section selects the fine resolution,high linearity cursor ring type TDC.An improved residual time extraction circuit is used between the middle and low TDCs for high precision extraction of error time.In order to improve the stability of the system,the TDC quantization resolution of each segment of high,medium and low is generated by the closed-loop negative feedback of the two-stage DLL.The main stage DLL is used to generate a precise cycle clock signal and a uniform differential multiphase clock signal.The former provides an accurate counting period for the high segment TDC,and the latter provides accurate resolution for the middle segment TDC.The secondary DLL is used to generate the delay difference required for the low-order TDC,thereby accurately minimizing the small error time.By adopting the method of measuring the initial and final phases separately,thus effectively introducing the slip method.Using the averaging method to process multiple measurements can effectively reduce the quantization error.The combination of the sliding rule method and the averaging method makes the accuracy and linearity of the TDC of this paper reach a good level.Under TSMC 0.35?m standard CMOS process,the proposed TDC is designed,and simulated through Cadence.The final layout of the DLL-TDC system is 835?m×800?m.The test results show that the resolution and dynamic range of the proposed TDC can reach 29.8ps and 1?s respectively under the condition of 125 MHz reference clock and 3.3V supply voltage.Compared with the previous TDC,the range and resolution are effectively considered.The DNL is controlled between-0.3LSB and 0.4LSB,and the INL is-0.5LSB to 0.5LSB.Thanks to the combination of the sliding rule method and the averaging method,the TDC single-shot accuracy of this paper is up to 6ps,which meets the precision required for high-precision timing applications.Each test sample has good performance consistency,which proves the robustness of the design.