Design Of A Time-to-Digital Converter Based On Carry-in Lines Of FPGA

Time-to-Digital Converter(TDC)is a kind of circuit of measuring time,which can convert a continuous time signal to a digital signal,and to realize the digitization of time measurement.It is widely used in scientific experiments and engineering applications,such as Time-Of Flight(TOF),Positron Emission Tomography(PET),Laser,Randar,Oscilloscopeand so on.There are mainly two types of TDC.One is ASIC-TDC and the other is FPGA-TDC.Compared with long design cycle,high-cost and poor flexibility of ASIC-TDC,FPGA-TDC has short design cycle,low-cost and good flexibility.So with higher request to the precision of time interval measurement and the development of FPGA technology,the design of high precision TDC on FPGA is of great significance.This paper firstly introduces and compared the different design method of TDC,takes internal structure and resources of Xilinx Virtex-5 FGPA device in consideration as well,the overall design scheme is present.With Top-down concept of FPGA,the design mainly was divided into two modules: coarse counting module,fine measurement module.The counting module function is realizd by one counter counting the rising edge of the system clock,others counting the falling edge of the system clock and fine measurement function is realized by tapped delay line,DFFs,thermometer-to-binary code coding circuit and calibration circuit.In the design,dedicated carry chain(CARRY4)of Virtex-5 were cascaded as a tapped delay line,which usually can take 4 tapped outputs(CO0,CO1,CO2,CO3),the MUXCY is used as a basic delay element,but will cause complexer encoder circuit,more logical resource usage in view of ‘bubble errors' of the thermometer code caused by the CARRY4's fast carry look ahead,as well this structure of TDC with a little larger integral nonlinearity and differential nonlinearity will appear some zero-delay taps.This paper optimize the structure of the CARRY4,which take 2 tapped outputs(CO0,CO3),the MUX and one MUXCY and the other three MUXCYs are respectively used as a basic delay element,eliminating ‘bubble error',improving the encoding speed and saving logical resource.Calibration circuit adopts bin-by-bin calibratation by the means of code density test and calibration to the center of each tap.Start channel and Stop channel is respectively configured with three chains to measure a signal simultaneously.After averaging,giving the final measurement to furtherly improve the RMS measurement precision.Finally the test platform was bulit in Xilinx Virtex-5 ML507.The LSB,DNL and INL of six chains of Start channel and Stop channel were analyzed and compared with chain of no optimization,the LSB of each chain is about 30 ps,the DNL of of each chain is about(-1,2)LSB and the INL of each TDC chain is about(-1,6.5)LSB;the LSB of chain of no optimization is about 14 ps,the DNL is about(-1,7)LSB and the INL is about(-2,16)LSB,which illusrates the chian of optimization has better stability and linearity.When using 3chains(M=N=3)measured on each chain,the RMS was tested to be 13.2ps.