Design Of A High Resolution And Multi-channel Time-to-Digital Converter Based On FPGA

Time-to-Digital Converter(TDC) is used for precise time interval measurement. Usually, it can achieve a resolution of sub-nanosecond. It is widely used in scientific experiments and engineering applications, such as satellite navigation, high energy physics experiments, medical imaging system and so on. The measure precision of the TDC is closely related with the advanced technology level of these applications field. Some of the applications need to use the multi-channel TDC to Improve the efficiency of measurement. There are mainly two types of TDC. One is ASIC-TDC and the other is FPGA-TDC. Though ASIC-TDC has excellent performance, its disadvantage is long design cycle, highcost, complexity and poor flexibility. With the development of FPGA device's process, FPGA-TDC can achieve a better performance as well, and in the meantime, it has the advantage such as short design cycle and good flexibility. So, the design of high precision TDC on FPGA is of great significance.The general design method of TDC was analyzed and compared in this thesis. According to the characteristics of the different structure TDC and the internal logic resources of Xilinx Virtex-5 FGPA device, a multi-channel high resolution coarse-fine TDC was present in this thesis. The coarse counting function is realized by the gray code counter and the fine counting function is realized by the tapped delay line. To achieve a high resolution, the dedicated carry chain(CARRY4) of Virtex-5 were cascaded as a tapped delay line. In view of the CARRY4's fast carry look ahead module will cause bubble errors of the thermometer code, the thermometer-to-binary code coding circuit is improved. In order to reduce the influence of process, voltage, temperature and system nonlinearity on the measurement accuracy, the measurement results were calibrated by the means of code density test. At the same time, this thesis designed a circuit to monitor the changing delay time of delay unit and avoided unnecessary calibrations. The TDC is configured with four measurement channels. By using layout constraints and manually layout method, four channels are arranged in parallel to reduce the measurement errors between difference channels.To verify the function and test the performance of the TDC realized, a lot of experiments are carried. The testing results showed that: The difference among the delay time of delay unit which placed in the same positon of four channels is really small. The average resolution of a signal channel is about 14.7 picoseconds. The differential nonlinear and integral nonlinear are 5.8LSB and 12 LSB. The larger nonlinear caused by the inhomogeneity of delay unit's delay time. A code density test circuit was used to calibrate the Non-Liner tapped delay line. After calibration, the RMS measurement precision of the TDC system is 25.5 picoseconds. Each channel obtained a RMS measurement precision of 18 picoseconds.