Design And Research Of Signal Multiplexing In FRAM Memory Array

In order to cope with the current bottleneck in the development of memory technology,the design and implementation of large-capacity,high-speed and reliable non-volatile memory has become a new research hotspot.As the main module of FRAM,the design of memory cells and array organization determines the overall performance and power consumption of FRAM.Through theoretical analysis,the realization and optimization of storage structure and array architecture are investigated,and specific control signal line optimization method is proposed to solve the signal multiplexing phenomenon caused by capacity expansion,which lays a foundation for the design and implementation of high-performance FRAM.Firstly,The design of array layout in expansion design is investigated,and an array partition structure to reduce the interference between signal multiplexing is proposed.From the theoretical point of view,the influence of the open-bitline architecture and the folded-bitline architecture on the array noise and the interference of three kinds of plate line architectures on storage cells are compared.Aiming at the influence of threshold loss and bit line capacitance during array read and write,a method of offsetting threshold loss and bit line load capacitance matching method using sense amplifier or bootstrap circuit is proposed.Then,specific control signal line optimization scheme is selected for signal multiplexing problem.Firstly,the influence of the three pulses of the plate line on the polarization of the ferroelectric capacitor is compared.The selection of the double-pulse driving method can simplify the circuit design and prolong the service life of the ferroelectric material.The hierarchical structure circuit of the plate line is designed to alleviate the influence of the load capacitance of the plate line.Then,it is determined that the charge pump circuit is used in the array structure to generate the word line voltage,and the ferroelectric capacitor is selected as the boost capacitor to provide a capacitor with a large capacitance at low power supply voltage and a small capacitance at high power supply voltage to optimize V_WL,the two-stage voltage of the wordline is optimized by the word line simulation circuit with load capacitance,so as to achieve the purpose of obtaining the optimal wordline voltage and reducing the power consumption of the array organization.In addition,in the bit line design,bit line optimization technologies such as pre-charge technology,auxiliary discharge circuit and balanced circuit optimization are used to improve the read and write efficiency of the array organization.A bit line simulation circuit is designed to evaluate the influence relationship between the ferroelectric capacitance and the parasitic capacitance of the bit line,and to increase the parasitic capacitance of the bit line by expanding the area of the ferroelectric capacitance or increasing the size of the switch transistor gate width of the memory cell,thus the optimal bitline performance is obtained.Finally,two staggered designs are proposed to reduce the noise of the signal lines in the array structure,alleviate the polarization fatigue effect of the ferroelectric capacitor.Finally,based on the above research,three parallel read and write FRAMs with different capacities are designed.The array organization adopts the array partition design,the folded bit line structure and the plate line hierarchical design,using the double-pulse driving method and the optimized word line and bit line design.Then complete the circuit layout and pre-and post-imitation.