Research On The TFET Cell Library Design Technology

To be one new shape of lower power consumption devices, TFET use the asymmetrical doping of source and drain to achieve energy band offsets, which penetrated the tunnel device working principle. TFET 's sub-threshold slope can be able to break through the 60 mv/dec limits, which means it can get greater switch current ratio, so as to achieve the goal of ultra low power consumption.Digital standard cell library(SCL) is the key of IC automation, bridging the physical realization and code design. Based on MOSFET SCL technology, this paper has research the develop direction of TFET, and research the method to apply TFET into the digital standard cell library. On the basis of existing technology, and using the specific TFET model provided by University of Notre Dame, we carried out relevant research on library unit design, layout plans and device detection.Based on traditional MOSFET devices, we carried out the digital standard cell library design, which contains the library unit schematic extraction and optimization, simulation, and layout design. In addition, we complete the process of building SCL, includes the most important type of library files and have wrote the corresponding scripts of the building process by using the existing library units.Under in-depth study of the combinational and sequential logic circuits, also the TFET device models, we select specific architecture of the unit circuit to avoid the effect of the TFET passing gate in the unit design. In addition, considering the compatibility issues of existing models, we designed an implemented circuit to test trigger time and hold time by using double clock edge.We also planned the cell layout, which based on the SCL rules and the specific layout model which have be tape-out tested. Then we researched on the DRC rules of the TFET layout, to achieve the goal of DRC testing of general TFET structure and special TFET structure which contains Pocket and Underlap structures.