A Research On The Fast Correlation-based Background Digital Calibration Techniques For The Pipeline ADCs

In SoC era, with the development of the CMOS process, the design of data convertersintegrated in the system chips is faced with unprecedented challenges brought in by scalingtheory and lower supply voltage, which result in more obvious nonideal effect, decreasedsignal dynamic range, increased power consumption, restricted signal bandwidth, instabilityand increased cost, etc. The thesis researches digitally assisted design technique for highperformance ADC. It can reduce design constraints of the high performance ADC existed inarchitecture, process, performance, area and power consumption with the aid of thecompleteness of digital signal processing knowledge and the advantage of large scaleintegrated digital circuits in the process, area and power, and then improve the performance ofanalog circuits.At first, this thesis summarizes the universal system architectures, general designprinciples and the design process of digitally assisted design technique adopting digital signalprocessing knowledge. Taking the pseudo-random sequence injected background digitalcalibration techniques as an example, thorough studies are put forward, including the basictheories and optimum algorithms of the digital calibration techniques and a series of importanttechnical problem from system level to circuit level. The digital calibration technique cancalibrate errors and eliminate non-ideal effects in a continuous way, and is not sensitive to theoutside interferences and the input signals.Secondly, aiming at the problem of slow calibration speed of the pseudo-randomsequence injected calibration techniques, the thesis then makes frequency domain analysis andbuilds the mathematics relationships between the correlation algorithm and the powerspectrum. The conclusion is drawn that the effective method improving the calibration speedis to decrease the amplitude of the correlated interference voltage. In order to quicken thecalibration speed, two fast calibration techniques of ADSC-modulation architectures areproposed on the basis of the frequency domain analysis, which are digital MSBs clippingtechnique and configurable double convsersion technique. Different techniques have differenteffect of reducing the amplitude of the correlated interference voltages and improving theconvergence speed of interstage gain.At last, the key circuits of the pipeline ADC with digitally assisted design technique aredesigned, including14bits100Msps sample-and-hold amplifer,3.5bits/stage MDAC withBi-direction overflow detection, sub-ADC with pseudo-random sequence injection, etc.