Low Power-Consumption Backend Design And Implementation Of A 28nm Graphics Processor

Throughout the history of Graphics Processing Unit,with the development of electronic technology,GPU performance and reliability has been greatly improved,the main frequency and circuit size of the circuit towards a higher and larger direction,at the same time,the performance and reliability of GPU have been greatly improved,so it has been widely used in people's daily work and life.In the traditional GPU design process,the optimization goal usually only includes the chip power consumption,the area,the time delay,the line length and so on.With the increase of GPU user's requirement and the improvement of manufacturing process,the existing GPU is faced with many problems such as how to divide the voltage domain,how to minimize the power network wiring area and how to optimize the clock tree.Based on Cadence's Edi10,QRC and Voltus tools,a 28 nm graphics processing unit chip is selected as the research object,the low power back-end design of the chip is studied in detail from the aspects of literature collection,design scheme analysis,logistics verification,and so on,the rationality and correctness of the solution are verified by calculation and simulation.The main work of this paper includes:The classification and basic flow of the back-end design are expounded in detail by collecting relevant research literature,then the corresponding low power design techniques are listed according to different power consumption types,and the concrete design scheme of integrated chip layout and low power clock tree is given according to the above theory.On the basis of the completed design scheme,various standard cell placement,clock tree network optimization and clock tree network layout of the chip are analyzed in detail by combining with design tools,finally,the layout,design rules,circuit rules and antenna effects of the GPU chip are verified by the simulation of DRC,congestion and timing optimization.After completing the above work,in order to get the concrete method to reduce the influence of metal filling on the working time sequence of the chip,Calibre and EDI10 are used to carry on the metal to the chip respectively,and the working time sequence of the chip before and after filling is simulated and analyzed,and came up with an effective method.In order to verify the correctness and rationality of the Low-power electronics and clock tree optimization scheme,the network parameters of the clock tree before and after the scheme and the power consumption of the chip are simulated,the simulation results of low power consumption,clock tree and integrated function of the chip are analyzed in detail,and the correctness and rationality of the design method are verified.