Research And Implementation Of Physical Design Methodology For Multi-Level Filter Chip

In deep submicron era, IC design in physical design has more and more challenge, with the increasing design scale, faster clock frequency and minimizing process dimension. Increased scale and more intellectual property (IP) used make interconnect increased and then bring trouble on floor-planning. Decreased process dimension makes the parasitic RC model of the interconnect more and more complex, result in the wire delay has a higher proportion of the total delay. Higher work frequency makes timing convergence more and more important, timing optimization becomes the main objective of the design. In this thesis, through the physical design of the multi-level filter based mini-object infrared image processing, floor-planning of the design, power analysis, parasitics abstract, timing optimization, clock tree synthesis and physical verification are discussed in detail. The main work of this thesis as follows: Firstly, introduce the theory and algorithm of current floor-planning method, and justify the floor-planning of this design in practice. Get a satisfied floor-planning result, using timing-driven floor-planning method. Secondly, analysis parasitics of the circuit in detail, and do clock tree synthesis for the clock to minimizing clock skew, optimize the timing violations by buffer insertion and gate resize, satisfy the timing requirement. Thirdly, describe power networks design methodology of the design, analysis IR drop and electromigration, and justify wire width of the power ring and power mesh in terms of the result of power analysis, and then get a better result. Finally, check design rules which is provided by foundry SMIC, including DRC, LVS, and ERC and fix all of violations. And fix poly density violations. This design is finished by 0.35 micron process technology of SMIC. All the physical design is accomplished and taped out for SMIC to manufacture.