Research And Realization Of H.264Video Compression Coding System Based On FPGA

H.264is the newest generation video compression encoding standard developed jointly by ITU-TVideo Coding Expert Group(VCEG)and ISO/IEC Moving Pictures Expert Group(MPEG). The newstandard introduces some advanced video encoding technology,including intra prediction,multi-frameinter estimation,1/4fractional pixel motion estimation,4×4integer conversion,entropy coding basedon the context,etc.As using these advanced technology,H.264has the merits of a high compressionratio,high image quality and good network compatibility.It has a widespread application in digitaltelevision, real-time video communication,network streaming multimedia and other various aspects.However,the computation complexities of H.264is very large,which will lead to great challenges forhardware implementation.FPGA is an important platform of developing video codec,because itfollows the advantages of large-scale,high integration and high reliability from ASIC,and overcomessome disadvantages of ASIC, such as the long design cycle,high investment and lack of flexibility.Based on deeply studying H.264encoding algorithm,a system of video capture and H.264encodingis designed on the Actel’s CoreMP7development board.A detail coding process is introduced.Thehardware structure of all main modules are designed,and some of which are realized on FPGA anddone functional simulation.The paper mainly includes the following several aspects:1.The system structure of video capture and H.264encoding is designed;meanwhile,the detailprocess and hardware structure of video capture is designed based on OV7670.2. The intra prediction technique is dicussed in details.A general processing element(PE) isintroduced which could be used in all prediction models.Based on the PE and the parallelcharacteristic of FPGA,a parallel hardware structure for intra prediction is designed.3. The inter prediction is dicussed detailly.The UMHexagonS algorithm for motion estimation isemphatically studied and improved in many aspects.The improved algorithm can save about7%~14%motion estimation time than the original one.Based on the improved UMHexagonS algorithm,amodule for motion estimation is designed.4. Transform and quantization are studied,including integer DCT,IDCT,Hadamard,IHadamard,allquantization methods and all inverse quantization methods.All hardware structures in this part aredesigned,realized,and done functional simulation on ModelSim.5. The principle of entropy coding is introduced in details.The coding processes and hardwarestructures of Exp-Golomb coding and CAVLC are designed.All the designs are realized on FPGA anddone functional simulation.