H. 264 Frame Prediction Algorithms And Hardware Design

High-speed-television Measurement and Recording (HMR) system is an important partof the modern shooting range measuring system. With the feature of high frame rate, highresolution and large amount of data, the modern HMR is usually designed withmulti-sub-station and network data transmission, as a result, the real-time transmissioncondition is essential in design process. Thus, choosing an appropriate video codingalgorithm to compress the captured data first is a meaningful approach to achieve thereal-time transmitting condition. As the latest achievement of video coding standard, H.264video coding algorithm increases the efficiency of video compression with a little imagequality lossless. Meanwhile, the hierarchical design of H.264enhances the adaptability ofdata transmitting via network yet. However, the enhancement of compress efficiency is paidby huge computation, which is not conducive to real-time applications occasions; therefore,reducing its computational complexity is an important part of H.264study.One of the main ideas of this paper is designing a coding efficiency improvementalgorithm to reduce the complexity of the intra prediction algorithm, by in-depth research ofthe H.264coding system. The proposed algorithm is tested by comparison with the originalalgorithm. Meanwhile, the other idea of this paper is designing a FPGA-based hardwarearchitecture of intra prediction algorithm. The hardware architecture is designed by top-downmethod and functional modules classification method, and simulation verification viaQuartus.