Video Encoder Design Based On FPGA

It starts the new era of the application of video communication and storage afterthe introduction of a series of international standard of video code that ISO å'Œ ITU-Testablished. All the time the goal is a common constant pursuit that achieving thequality of picture as good as possible on the basis of code rate(or memory capacity) aslow as possible from the suggestion of H.261 video code to H.262/3,MPEG-1/2/4video code ,etc.The research of this subject is set up on the basis of the mainstream compressionalgorithm at present, integrates the generality and advantage of realization approachfrom various kinds of standards, and transplants the subject of algorithm on theplatform of FPGA (Field Programmable Gate Array). It also relies on the abundantand flexible characteristic of embedded system to set up the reconstructed module ofkernel disposing. And after the further consummating of algorithm (operation speed,precision) and peripheral system, it can be the antitype to carry on the gate levelcircuit design for the special-purpose encoder of video compressing, and to make upthe independent System On Programmed ChipIt has good application prospects of the encoder designing. It compresses thecode of moving picture from the space through using the varying of dispersed cosineand entropy code to make the coded dataflow suit for the request of transmit,communication, storage and editing. Meanwhile, the systematic design reduces a largemargin of the work load of decoding;the functional module can be the design ofdecoder for the reference to use after doing the proper change.Every module function that the research involved has carried on systemic emulationand synthesis. They can meet the earlier researching and developing need of theengineering model.