Behavioral Model And The Key Components Design Of A High-Speed Data Acquisition ADC

Analog-to-Digital Converter(ADC) is the key component of a Data Acquisition Sys-tem(DAS), as the ADC's performance is the main restriction of the DAS, especially on the sampling rate and the resolution. In some circumstance, there is no need to use high resolution ADCs. For example, in the Ultra-WideBand(UWB) communication design, the FLASH ADC is enough. The Top-Down design flow has been widely used in the mixed-signal design field. As an important aspect of mixed-signal, it is quite an important approach to build the behavioral model of the ADCs to raise the efficiency of designing and simulation.Based on the former analysis, a 4-channel time-interleaved FLASH ADC's behavioral model was built using Matlab&SIMULINK tools, and the error from channel mismatch was simulated. And then, a 4-bit, 4-channel time-interleaved architecture of FLASH ADC was proposed, with each channel running at 1GHz clock. The key segments of the ADC, including Sampl- ing/Hold(S/H) circuit, high-speed comparator and the thermometer-to-binary encoder were designed and their layouts were finished. All the design and implementation has been finished using the 0.18um CMOS process of the Smic.Inc.