Based On The Nios Ii High-speed High-precision Data Acquisition System

With the development of modern radar and communication systems, the data acquisition system needs work at higher sampling rate and precision. Limited by ADC chip's manufacturing process, It is hard for a single ADC chip to acquire the high sampling rate and precision The parallel times-interleaved sampling ADC system is an effective way to increase the sampling rate. The time interleaved ADC system works as: M parallel ADCs work with a sampling frequency fs / Mand the system output are multiplexed together. This gives an overall sampling frequency f s. The drawback with this structure is that, the channel mismatch errors will occur in the system. The mismatch errors mainly include time errors, gain errors and offset errors. This means that the signal will be non-uniformly sampled. These mismatch errors will degrade the system performance if they are uncorrected. And it is very difficult to provide precision times-interleaved sampling clock to parallel sampling.An explicit analysis of such three channel mismatch errors is discussed in this paper. We presented the algorithm of measure errors combined three errors and the effective algorithm of calibration based on FARROW structure. At last,this paper solve the difficult of the implement of the clock of times-interleaved sampling system. Based on these theory, design and research a high sampling rate and precision system, the system's highest sampling rate can reach 240MHz。The debug results indicate that it can improve the performance of the system. The primary works in this paper are presented as follows:1. The creative and useful algorithm was presented to measure and calibrate the three mismatch errors by explicitly analyzing the three mismatch errors in time-interleaved sampling system. And the effective calibration algorithm based on FARROW structure.2. To complete the parallel data acquisition system with 240 MHz sampling rate made up of three AD6645. using clock management chip AD9512 to achieve the clock of parallel sampling, and compute the channel mismatch errors on the NiosⅡ.3. To complete the system performance analysis according to simulation and test. It's ENOB can reach 9 bit.