Co-simulation And Co-design Of DDR3 System Based On Creative CPU

In the realm of modern high speed digital system design, signal integrity problems are becoming more and more outstanding, and the design on chip, package and system is facing tremendous challenge. The current server platform commonly use DDR3 to improve the memory access speed and bandwidth. DDR3 is typically parallel bus structure, with lower power supply voltage, higher data transmission rate, simultaneously also reduces the system noise tolerance, the data window timing margin, and increases the interference between adjacent networks. Die, Package and PCB board level system design have increased the difficulty, or even became a bottleneck for DDR3 to further improve the transmission rates.In order to ensure that the DDR3 system could achieve the design goals and work stably, this paper studies the DDR3 protocol and interface design technologies thoroughly,and combined with the actual engineering requirements, designs and implements the DDR3 interconnect interface based on critive CPU server platform through SI and PI co-simulations under multiple models,multiple design environments. Innovative works are as follows:1) Establish the chip, package, PCB and DIMM daughter board co-simulation model for the full channel of DDR3 system.2) Study a series of key works as follows,the I/O Buffer driver strengthen, DDR3 data signals topology structure and ODT termination strategy, optimization of multilayer PCB vias, system power plane and target impedance design, simultaneously switching noise influence etc. Quantitative analysis and calculation the factors affecting the DDR3 timing.3) Create the test platform for the actual system to the signal integrity tests and verify the correctness of the simulation,and provides further optimization proposals and measures for independent CPU design, PCB layout and interconnect design.The researchs on the subject provide design guidances which can shorten the research and development cycle and reduce costs for the server platform DDR3 system ,and the design of the DDR3 system achieve the expected design goals.