Research On High Frequency Dynamic Coded Signal Acquisition And Storage System

The data acquisition and storage system is indispensable in the field of testing,the rapid development of information technology makes the transmission speed of the data stream higher and higher,which in turn drives the data acquisition and storage system toward high speed and large capacity.In this paper,according to the specific requirements of the laboratory project,a method for high-speed acquisition and storage of high frequency dynamic coded signals up to 50 MHz is proposed.According to the characteristics of the signal to be measured,the signal processing and sampling theory required for the study,from the signal transmission methods,chip selection,and the late circuit board stack structure and layout and wiring,planning a specific hardware circuit module,the design of a high-speed acquisition memory circuit consists of power management,signal attenuation,high-speed ADC,high-performance FPGA,DDR3 cache,and eMMC storage.The circuit design is completed on the Cadence platform.The schematic design is performed through OrCAD Capture CIS.The simulation circuit of the designed attenuation circuit is combined with Pspice.The transmission line effect is studied for the reflection of high-frequency signals.Topological structure extraction and simulation of the PCB's key single-ended signals and LVDS signals multiple impedance matching methods are performed on the PCB SI platform.The optimal matching method is selected for comparison and analysis,and the use of capacitors in high-frequency circuits is simulated and analyzed.In addition,from the aspect of layout and wiring,specific improvements to signal integrity issues such as crosstalk,signal delay,and electromagnetic interference in high-speed circuits are proposed.In the design of system logic,rational use of internal hard-core resources of FPGA,such as phase-locked loops,FIFOs,and MCB and so on,simplifies development work and can accurately accomplish related functions.The system uses a negative delay sampling strategy to store part of the data before the start of the trigger to ensure the integrity of the valid part of the signal to be measured.After receiving the trigger signal,the data is first buffered into DDR3,and the data is transferred to the end after the acquisition.eMMC researches the operating specifications and timing of DDR3 and eMMC used in the system,and conducts simulation analysis on key read and write operations.Through reasonable hardware and logic design,a signal acquisition and storage test system with a sampling frequency of 500 MHz and an 8 bits width is realized,and simulation testing is conducted.Finally,the experimental test data is analyzed,and the designed acquisition system is further optimized according to the test results.