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Research Of High-speed And High-precision Time-interleaved ADC Calibration Technology

Posted on:2022-12-22Degree:MasterType:Thesis
Country:ChinaCandidate:R LiFull Text:PDF
GTID:2518306764479604Subject:Computer Software and Application of Computer
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Analog to Digital Converter(ADC)is an important bridge connecting the analog world and the digital world.It plays an indispensable role in modern electronic communication systems,medical technology,instrumentation and control and other fields,and has an important strategic role.significance.However,there is a trade-off relationship between the sampling rate and the number of resolution bits of the ADC,that is,under the same design level and process conditions,the higher the sampling rate,the lower the number of resolution bits,which limits the ADC to achieve high speed and high precision at the same time.direction of development.Among the many ADC structures,the pipeline ADC structure stands out,achieving a good compromise in sampling rate and resolution,and becoming one of the optimal ADC structures that takes into account both high sampling rate and high precision.Due to the limitations of analog circuit design,semiconductor technology and input bandwidth,single-channel ADCs are increasingly unable to meet the requirements of high-performance ADCs for ultra-high-speed systems.In order to overcome the speed limitation of the traditional single-channel ADC and take into account the accuracy,the use of multiple ADCs alternately sampling in parallel(time-interleaved ADC,TI ADC)has become an inevitable trend to break through the performance bottleneck of the single-channel ADC.Although the time-interleaving structure can improve the overall speed,the mismatch between the channels will also affect the overall performance.The mismatch between channels of TI ADC mainly includes:offset mismatch,gain mismatch and sampling time mismatch.In a time-interleaved ADC,channel-to-channel mismatch causes corresponding spurs to appear in the spectrum output by the ADC,reducing the overall performance of the time-interleaved ADC.These channel-to-channel mismatches not only limit the ADC's spurious-free dynamic range(SFDR),but also severely reduce the resulting effective number of bits(ENOB).Therefore,in order to improve the performance of the TI ADC,the TI ADC must be calibrated within and between channels.Among them,the calibration of offset mismatch and gain mismatch is relatively mature,and the technical difficulty lies in the calibration of sampling time mismatch.This thesis firstly introduces the single-channel pipeline ADC structure,and performs intra-channel calibration for the single-channel ADC,mainly including capacitance mismatch,inter-stage gain and comparator offset calibration.For the calibration of the three-term mismatch(gain,offset,time?skew)between channels in a single-chip ADC,this thesis adopts a digital-analog hybrid method: pure digital calibration for offset mismatch and gain mismatch;digital domain extraction for sampling time mismatch Error,the calibration error in the analog domain(using a variable delay line,Variable Delay Line,VDL).To achieve higher speeds,this can be achieved by interleaving at the board level with multi-chip ADCs.For inter-chip mismatch calibration of multiple ADC chips,the inter-chip mismatch is roughly similar to the inter-channel mismatch,but there are more uncertain factors.The inter-chip offset mismatch and gain mismatch use pure digital calibration;the sampling time mismatch uses the digital-analog hybrid method to complete the rough calibration,and uses the off-chip delay filtering method to achieve the fine calibration.The calibration in this thesis is applied to the 12GSps12 Bit ADC interleaving board,which can increase the spurious-free dynamic range(SFDR)by31.3564 d Bc on average,and the effective number of bits(ENOB)by 3.1776 bit on average.
Keywords/Search Tags:ADC, time interleaved, pipelined, delay filtering, calibration
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