Research On NBTI And HCI Effect Of GAAFET At 7nm Technology Node

When the characteristic size of device continues to shrink to the deep sub-micron level,the performance of traditional planar MOSFET devices severely degrades due to the short-channel effect.The non-planar FinFET structure has become a widely used device below the 20nm process node.With the continuous development of integrated circuit technology,the size reduction of the FinFET structure is further limited.The gate-all-around field effect transistor?GAAFET?is widely considered to replace FinFET below 5nm process node due to its stronger gate control ability and the ability to suppress short channel effect.At the same time,it is well known that device reliability is a key factor to limit the performance of circuits.The new structure and process of GAAFET brings up lots of new features which affects its reliability.Therefore,studying the reliability of GAAFET devices and analyzing the failure mechanism are crucial to the design of high-performance and high-reliability integrated circuits.In this paper,we firstly evaluated the device performance of deep-nano FinFET and GAAFET,and then analyzed the NBTI effect and HCI effect of GAAFET device,respectively.The major contents include:Firstly,Sentaurus TCAD was used to compare the static,dynamic and reliability characteristic of FinFET and GAAFET with different nanowire shapes at 5nm and7nm process nodes.The results showed that the driving current of the device can be increased from 12.844?A to 40.318?A by increasing the nanowire number of the vertically stacked GAAFET,whereas the DIBL and SS decreased from 47.11 mV/V and 76.58 mV/dec to 53.19 mV/V and 78.41 mV/dec,respectively.Moreover,the gate control capability and DIBL of GAAFET were better than the counterpart of FinFET at the same process node.However,the GAAFET shows disadvantage over the dynamic characteristics and reliability,which is related to shape of nanowire.The cylindrical and rectangular nanowire have the different V_thh degradation caused by the NBTI,giving 54.36 mV and 64.58 mV,respectively.Secondly,the impact of NBTI effect on 7nm GAAFET device is performed with Sentaurus TCAD.In order to understand the influence of interface states on the NBTI effect,the role of single donor interface trap and different spacer are thoroughly investigated.The results show that?1?by introducing even one single trap,the different spacer lead to different influence on I_off,the SiO₂ and HfO₂ spacer show different relative degradation of I_off,giving 21.94%and 13.15%,and the degradation of V_thh induced by NBTI effect are 60.1 mV and 51.8 mV,respectively.?2?The different position and energy level of the single trap may introduce significant shift in the characteristic of GAAFET.When the trap resides in the central channel,the relative shifts of V_thh and I_offff are 10.53%and 36.12%,respectively.Moreover,it is easier to capture holes when the trap level is close to the conduction band,so that the relative shifts in V_thh and I_offff reach 19.43%and 66.13%,while the relative change of gate capacitance is less than 1%.?3?when source-drain voltage was increased from-0.7V to 0V,the V_thh degradation caused by the NBTI effect were reduced from 66.6mV(V_ds=0 V)to 61 mV(V_ds=-0.7 V)by 5.6 mV,and the degradation can be deteriorated by increasing temperature and stress voltage.Thirdly,the HCI effect of 7nm GAAFET devices is thoroughly investigated.The results show that?1?the HCI effect has greatest influence on the characteristic parameter in saturation region.?2?The maximum channel power density?244 W/cm²?and the rate carrier collision ionization(6.21e²77 cm^-3s^-1)in the drain region were reached at V_gs=V_ds=-0.7 V,so that the V_thh degradation affected by the HCI effect is27 mV.?3?reducing the device size and increasing the doping concentration will lead to more serious HCI on V_thh and I_on.Increasing the spacer dielectric will mitigate the peak electric field from 7.18e⁵ V/cm?SiO₂?to 6.15e⁵ V/cm?HfO₂?,which is effectively to suppress the HCI effect.?4?Different bias condition lead to different degradation,for a given stress time of 10³ seconds,the relative degradations of V_thh are8.78%@V_gs=V_ds=-0.7 V and 16%@V_gs=-0.7 V&V_ds=0 V.In summary,this work can provide the important reference for the structural design,process and reliability modeling of GAAFET devices in deep nano era.