Goi And Nbti Reliability Of Deep Submicron Devices

With continuing development of semiconductor technology, the transistor dimensions are keeping scaling down from sub-micron to nanometer technology. According to the Moore's Law, the number of transistors or memory bits is doubling every 1.5 to 2 years. With the gate oxide thinning, channel length shrinking and etc. for the down-scaling, the critical electrical parameters of CMOS devices, such as threshold voltage shift, Gm degradation, gate/drain/substrate current and junction leakage, are getting worse and worse, and thus strongly impact device lifetime and limit the further development of the technology node.In this work we conduct the reliability test of Gate Oxide Integrity (GOI) and Negative Bias Temperature Instability (NBTI) and will focus mainly on the failure mechanism, the relative test methodology, test flow, test key and data analysis. Furthermore, the statistical process control method of semiconductor manufacture is also developed.As we know, oxide breakdown is one of the most threatening failure mechanisms in integrated CMOS circuits. By now, the oxide thickness is shrinked down to about 10(?) in the 65nm technology node, the breakdown definition itself is no longer clear and its detection becomes problematic due to incleasing quantum tunneling effect. Therefore, how to reduce the noise background to catch the accurate breakdown point and how to evaluate the device lifetime for ultra-thin gate oxide is a big challenge in GOI reliability test. Some novel methodology improvement including test methodology improvement and test data analysis are investigated in this work.Besides GOI reliability concern, negative bias temperature instability (NBTI) of p-MOSFET has been indentified as a critical limiting factor that ultimately determines the lifetime of the devices in deep sub-micron technology. In this work, we will also discuss the NBTI test flow and modeling. As saturation and self-recover effect have been found in p-MOSFET NBTI test, some new fast test methods based on recent device physics research have been introduced. Finally we developed our own integrated reliability test methodology based on industry standards and our research results in GOI and NBTI, which provides the reliability assurance for semiconductor mass production.