Circuit-level Investigation Of NBTI Effect

With the continous scaling of transistor dimensions, negative bias temperature instability (NBTI) has become an important factor for reliability of MOS devices. It is reported that the lifetime degradation of devices induced by NBTI is more serious than Hot carrier effect. NBTI will limit the lifetime of devices eventually. After further research on the degradation mechanism and process improvement of device-level NBTI, circuit-level NBTI and circuit reliability design has become a new research hotspot.Based on the 0.18?m CMOS test chip provided by Shanghai Hua Hong NEC Electronics Co. Ltd., an in-depth study on dynamic NBTI effect and the impact NBTI on the performance of digital circuits is investigated. In the study of the dynamic NBTI effect, it is found that parameters of the device degrade and the voltage threshold shift (ΔVth) follows the same power-law relationship with NBT stress time as the static NBTI effect under the same stress conditions. Howrver, the threshold voltage shift (ΔVth) is less than the static NBTI effect. Experimental results show that the threshold voltage shift (ΔVth) is independent of frequency under low frequency(<100KHz) stress, but the lifetime enhancement increases monotonically with smaller duty cycle. Based on the static NBTI effect model and the reaction-diffusion (R-D) mechanism, a expression was derived for the threshold voltage shift under dynamic operation. Model accuracy and efficiency were verified with the experimental and simulation data and this model can estimate the lifetime of devices.Based on the study on dynamic NBTI effect, the impact of NBTI on the performance of digital circuits is further investigated. In this paper, HSPICE simulations of 0.18?m digital logical cells and the ring oscillator circuit are performed. It is found that the degradation in delay is less than the degradation in the threshold voltage. The impact of NBTI on the delay of the different logical gates are different under the same gate input. The delay time rate of NOR gates increases 4.17% with 20mV Vth shift, while it increases 2.29% in NAND gates. The NBTI-effected delay and frequency degradation of a ring osillator circuit increases as the supply voltage.