The Research Of NBTI Precise Modeling In Nanometer MOS Devices And It's Reliability Prediction Technology

With the rapid growth of new fields such as Autopilot,Cloud Computing,Industrial Io T(Internet of Things),Artificial Intelligence and so on,the usage model of chip is being changed dramatically.It is well known that device reliability is essential to chip level reliability,so the failure of devices will have a strong influence in the lifetime of chip.For example,today's automotive chip is in the idle 90% to 95% time,while the idle time of chip in future autopilot will be only 5% to 10%.This kind of change requires that the chip must have higher reliability level within the same lifetime,which brings an extremely big challenge to the reliability-aware design in integrated circuits.On the other hand,with the cost increasing in the R&D and manufacturing of nanometer CMOS technology,there will be a huge financial loss due to chip failures caused by unacceptable reliability level.Meanwhile,with CMOS feature size scaling down to sub-nanometer,thousands of new materials,new technologies and new structures have raised high demands for the research of Negative Bias Temperature Instability(NBTI)effect of PMOS devices.The non-uniformly distributed interface traps,the stochastic degradation introduced by single trap response,the adoption of high-k materials,and the complex and variable operation modes of circuits,so many factors bring new challenges to the in-depth understanding of NBTI effect.Therefore,NBTI failure mechanism,reliability time-domain model,chip-level reliability simulation and aging prediction in nanometer MOS devices have been a very hot topic in both academia and industry in recent years.This thesis focuses on the research of NBTI precise model in nanometer MOS devices and chip-level reliability prediction technology.Through the analysis of the mechanism in nanometer MOS devices,the characteristics of non-uniformly distributed interface traps,the degradation behaviors under dynamic voltage frequency scaling(DVFS)operations,and on-chip reliability monitor have been deeply investigated.The main achievements in this thesis can be summarized as follows:1)The new characteristic of non-uniformly distributed interface traps in Si/Si O2 gate oxide which behaves itself as an exponential function of channel length from center to edge was found in recent years.The traditional NBTI model does not consider this geometry dependence,which causes a big limitation.In this thesis,the channel region was divided into 9 different regions,next,through the mathematical calculation,the device geometry dependence(L,W,d L,and d W)with only two fitting parameters(b1 and b2)was introduced.Besides the large size device,the new model also covered the small size device including narrow channel and short channel respectively,which made the model suitable for the different size devices thus extended its application range.Based on that,the NBTI degradation of different size devices was analyzed by using the proposed model.The results were as follows: i)a shorter channel width leads to a larger degradation;ii)the relative degradation is deteriorated with the longer exponential distribution length;iii)the device with smaller size degrades faster than that with larger size;iv)except for the small size device(Ldrawn<2d L,Wdrawn<2d W),the relative degradation is decreased when channel length becomes longer.2)Rather than a constant DC stress or a AC stress with a fixed pattern,the chip in real world is experienced with a great variety of operational stress modes.Therefore,the circuit NBTI aging prediction becomes more and more sophisticated.In this thesis,the degradation and recovery behavior of NBTI under DVFS was investigated.The traditional closed-form model based on RD and T/D theory has two limitations: i)the device to be predicted must be initially fresh at every stress/recovery cycle.ii)the stress/recovery pattern must be kept fixed,which means the voltage,frequency,duty cycle and temperature all are constant during the whole aging period.To get rid of these two limitations,a novel closed-form model was proposed through the rigorous mathematical deduction,and the related calculation method and flow were introduced as well.Given a certain stress condition under DVFS,the accuracy of aging prediction provided by the new model was improved 32% and 31% respectively,compared to the traditional RD and T/D models.The proposed model can provide a theoretical guide for the reliability-aware design in high performance integrated circuits under complex and variable operation conditions.3)In view of the modeling research being linked to the practice of circuit-level reliability prediction,the technology of on-chip monitoring of NBTI reliability was investigated.In this thesis,by revising conventional Schmitt Trigger 6-transistors structure,a novel NBTI aging monitor was designed,which realized a direct correlation between the threshold voltage degradation and the phase difference.The circuit has successfully achieved: i)the liner correlation between threshold voltage degradation ?Vth and pulse width is pretty good;ii)the measurement resolution can be real-time adjusted by changing the input slope;iii)the circuit is independent to process and voltage from the circuit principle.The prototype chip was fabricated on 1.1V,36 nm CMOS technology.The measured equivalent resolution was 3.4ns/m V under 1?s rise time sawtooth input,which was sufficient to suppress the unwanted fast recovery during testing.Moreover,the comparation of degradation results between the proposed circuit and the single device(W/L = 0.9?m/0.036?m)was performed.At 2000 s,the relative errors were 9.1% for 1.8V and 50 oC,and 5.7% for 1.8V and 25 oC.In a short,through carrying out an in-depth research on NBTI precise modeling in nanometer MOS devices and on-chip reliability monitor technology,several innovative results have been achieved in this thesis.These results make contributions to NBTI mechanism,modeling and testing from aspects of device geometry dependence,DVFSintroduced operation modes and on-chip monitor for aging predication,which will offer the practical value to the design of high performance and high reliability integrated circuits.