Design And Chip Research Of FFT Processor

After the downlink of the radar transceiver passes through the frequency conversion,the intermediate frequency signal needs to be further digitized in order to analyze the distance,speed,angle,etc.In this paper,the intermediate frequency signal of the radar receiver is processed to complete ASIC design of 256 point FFT processor.By studying several typical FFT algorithms,this paper chooses radix-4 algorithm and pipeline architecture to implement the processor.The entire system includes a control unit,an address generation unit,a data access unit,a butterfly operation unit,a rotation factor storage unit,an inverted sequence unit,and a modulo unit.The data format is:input 12-bit ADC sampling data,output 12-bit modulo value,the middle data bit width is 24 bits,the highest bit sign bit,15-bit integer part,8-bit fractional part.This design uses SRAM to store the input and output data and the data in the middle of the butterfly operation.The rotation factor uses a look-up table method.The butterfly unit uses Booth coding,4:2 compressor,and carry-forward adder,and finally uses an improved complex multiplier architecture.Through the combination of Matlab,Modelsim and VCS,not only the algorithm level is verified,but also the correctness of the circuit function is verified in the hardware design and physical implementation process.The physical implementation of the FFT processor is based on a 180nm 1P6M process.The synthesis stage is based on Synopsys'tool DC.It can work at a frequency of 100MHZ.After obtaining the gate-level netlist,it passes the netlist simulation.The back-end design is based on Cadence's Innovus back-end design software.It completes the layout planning of the entire chip,synthesizes the clock tree for the entire clock network,completes the automatic wiring through the tool,then completes the manufacturability rule check and post-simulation,and finally completes the physical Verification,including DRC and LVS,results in a final layout area of 3.3×2.2mm~2.