Research And Design Of TDC In High Precision Measurement System

The Time-to-Digital Converter(TDC)is the key circuit for measuring time intervals.It converts a small amount of time into a digital amount,and is widely used in high-precision measurement systems,digital phase-locked loop circuits and analog-to-digital converter circuits.The core of a TDC is to design a high-precision and high-reliability delay circuit.However,the precision,the range and the reliability of the delay circuits in traditional designs encounter challenges.To solve the above problems,a self-timed ring-based(STR)TDC is proposed for a high precision measurement system.A STR is designed to generate a number of evenly distributed oscillation signals with a fixed phase difference.A double-edge Gray counter array is proposed to measure the number of clock edges of each oscillating signal in the time interval for test.Using the parity and hamming block to reduce glitches in high-speed counting and realize the accurate measurement.According to the characteristics of TDC proposed in this thesis,an improved code density method is used to calibrate the phase difference of oscillating signals,and the calibration unit is designed and completed.The TDC circuit is simulated and verified on Modelsim and Spectre platforms,and realized on FPGA with primitive custom units manually placed and routed.In this thesis,the TDC design is implemented on Xilinx Virtex-5 FPGA,and the resolution(LSB)of 22.2ps is achieved with a 61-stage STR.The code density test result shows that the differential nonlinearity is about-1LSB to 1.52 LSB,the integral nonlinearity is about-6LSB to 7.48 LSB,the time precision is about 47.6ps,and 585 LUTs and 992 registers are consumed.The FPGA implementation verifies the TDC design method proposed in this thesis.The TDC resolution is expected to be further improved by increasing STR stages with appropriate initial value and apply the TDC circuit to a high-precision measurement system.