B3G FPGA Design And Implementation Of Key Technologies Of Ldpc Coding And Interleaving

During the past twenty years, in the whole world, mobile communication has been developed rapidly and undergone three generations—the first generation based on analog communication, the second generation based on digital communication, and the upcoming third generation based on multimedia communication. The development of each generation is determined by the breakthrough of technology and the innovation of concept.Nowadays there has been great development in the mobile communication all over the world. The government attaches importance to it and has started the"FuTURE project"named B3G-beyond 3rd generation mobile communication system (B3G). UESTC is in charge of the TDD downlink that bases on FPGA.Low Density Parity-Check (LDPC) Codes were first discovered by Gallager in the early 1960s and recently have been rediscovered and generalized. This class of codes decoded with soft-in soft-out (SISO) iterative decoding performs amazingly well. Since their rediscovery, design, construction, decoding, analysis and applications of LDPC coded have become focal points of research. Among them, the coding algorithm and its implementation design are the focus of this thesis.FPGA (Field Programmable Gate Array) is a kind of programmable logic device. By the programmable cable, we can download our design to the FPGA chip. Shorter designing time, less investment and no risk are the advantages and it can be modified, programmed and downloaded repeatedly.The purpose of this paper is studying the hardware implementation method of the coder of LDPC code, interleaver and various interfaces using FPGA. The FPGA chips use XC2VP70 of the Virtex-II Pro family product made by Xilinx Company and the Memorys use SDRAM made by Micron Company. The design platform uses ISE software family which is designed by Xilinx too. Based on the last research of LDPC algorithm of B3G, this paper emphasizes on how to design and implement the digital system of the whole algorithm. After simulation, the design was downloaded to chips and makes the link implement successful.