The Research Of Low Density Parity Chech Code Based On Fpga

LDPC(Low Density Parity Check Code)was initially proposed by Gallager in his doctoral dissertation in 1962, and it is also called Gallager code. It is a kind of linear block error-correcting code that is represented by very sparse matrix. Its performance approaches the Shannon limit, and both performance and costs of LDPC code are also better than Turbo code. Now it has been set as the preferred error correction program for the next generation of mobile communication by a number of communication companies. Therefore, in recent years, LDPC code has been become one of the hotest topics in the channel coding field. This paper discuss and study the LDPC code from both the theory and the hardware implementation, and finally finish the design of LDPC encoder.In the theoretical research field, firstly, this paper introduces the basic concept of LDPC code and its principles; Secondly this paper discusses and analyses construction methods of the LDPC code. Then, it discusses several LDPC encoding algorithms and means of its encoder, especially, based on approximate lower triangular matrix, it analyses the effective encoding method in detail, and improves this algorithm accordingly.Finally, on the QuartusⅡ7.2 software platform,the hardware implementation of LDPC is simulated,synthesized etc. with the Altera Corporation's Stratix series FPGA component EPIS25F672I7 devices, and realized the design verification. The simulation results show the clock rate achieve 120MHz, its performance satisfies the design requirements.