Design And Implementation Of High-speed LDPC Convolutional Code Decoder Based On FPGA

Low Density Parity Check(LDPC) is a kind of code with excellent performance, which has attracted tremendous attention in academic circles based on its near-Shannon limit error correction performance, low complexity decoding algorithm, and high parallelism hardware implementation architecture. Low Density Parity Check Convolutional Code(LDPC-CC) is a convolutional version of LDPC codes that draws a lot of attention for the characteristics not found in LDPC codes recently. In this paper, deep studies of LDPC-CC are performed based on its theoretical analysis and hardware implementation respectively, and eventually complete the design and implementation of LDPC-CC decoder based on FPGA.In this paper, we firstly introduce the basic encoding algorithm and describe the termination of LDPC-CC. Moreover, a feasible structure of the encoder is proposed. Secondly, we introduce several main soft-decision decoding algorithms and analyze the performance under different messaging mechanism. And the influences of different quantization schemes, code length are also simulated.Then, we give a hardware implementation architecture and describe the cutting technology and folding technology of the message storage scheme. An improved storage scheme is proposed to balance the registers and memory use. Moreover, a new scheduling strategy is proposed, which reduces the memory resources on the basis of the original. Finally, the decoder has been realized in Kintex-7 FPGA by using a top-down design pattern, the clock frequency of the decoder can be up to 200 MHz after placement and routing. Maximum information throughput 400Mb/s can be achieved under 18 iterations. Simulation results indicate the decoder can achieve less than 0.1dB implementation loss which can meet the requirements of the system.