The Design Of High Precision Coarse- Counting Circuit And Error Calibration Circuit For TDC

The main application of High-precision time-to-digital convert(TDC)measurement system is that used to convert the time interval between the occurrence of one or more physical events to digital quantities.And the measurement system has been widely used in high-energy physics experiment,global positioning system,laser ranging,medical imaging,etc.Therefore,the TDC measurement system plays an important role in various research fields.The implementation way of TDC measurement is varied,the method adopt in this paper is based on Xilinx Artix-7 FPGA to complement the design and implementation of coarse measurement part,delay-line,calibration module,and connecting with the part of fine measurement to complete this topic research.The calibration of measurement error is realized under the premise of ensuring the larger dynamic measurement range.The main work of this paper is as follows:(1)To investigate and summarize the application background and development prospects of TDC measurement system in various research filed.Considering the demand of high measuring accuracy in laboratory project that is single photon detector,so the research this paper is focus on that how to improve the precision of TDC measurement system.(2)In view of the integrated environment of TDC measurement system in the future design,a digital circuit implementation method is adopted to facilitate the integration of the time interpolation technology.(3)In order to optimize the measurement system architecture and facilitate the improvement of this design in the future work,this design adopts a measurement method that combining coarse measurement and fine measurement.And using Vivado to simulate the important modules in the system.Using the abundant logic resources which in the Xilinx Artix-7 FPGA to implemented the system that include the coarse measurement module,fine measurement module,pseudo-random number generation module and error calibration module.(4)Code density testing method is adopted in the design of delay chain module test.And get the nonlinear characteristics of delay unit.Analysis the characteristics data and resolve the nonlinear defect of delay time in delay unit.(5)Analyze the data of the code density test by MATLAB.And verify the feasibility of the design from the actual measurement data.A TDC measurement system is implemented based on Xilinx Artix-7 FPGA in this paper.The results of simulation and test show that,in the module of pseudo-number,the output data rate of pseudo-random number was upgraded from 0.86 Gb·s-1 to 3.16Gb·s-1 and the cycle of pseudo-random sequences was upgraded from 2n-1 to 2n compare to the method of De Burijn and Leap-forward LFSR;in the module of error calibration,the inherent error was reduced from [-22.6ps,41.8ps] to [-11.1ps,16.6ps] and the efficiency is approximately 72.5%;in the module of measurement system,the dynamic measurement range was 838 ps,the resolution was upgraded to 59 ps,the absolute error is reduced from 57ps~90ps to 38ps~74ps,the relative error control within 0.098%.In conclusion,the technical indicator of this design meets the requirements of measuring precision in each application field.