Research And Design Of Key Circuits For The High Speed Memory Buffer

With the rapid development of technologies such as big data,machine learning,real-time data analysis,and virtualization of heavyweight applications,the server field has placed increasing demands on memory capacity and bandwidth.The server-class memory module uses the memory buffer chip to buffer high-speed signals between the memory controller and memory chips,thereby supporting more memory modules and running at higher speeds.The paper studies the hold time issue between the input sampling clock and the output transmit clock that must be solved in the design of DDR5 RCD chip,under development.By studying the implementation method of fixed propagation delay,the cause of the hold time issue between the input sampling clock and the output sending clock is analyzed.By analyzing the simulation results of the relevant circuit over the target PVT range,it is determined that the design needs to handle the hold time issue caused by the clock skew of no more than 3 clock cycles.The paper puts forward the idea of data rate reduction,which designs a circuit structure that makes use of latches to implement serial-to-parallel then serially outputs the final parallel processing results,in order to solve the hold time issue of the timing path between the input sample clock and the output transmit clock that has a relative clock skew that varies with PVT.A sequencer circuit is designed to generate and synchronize the input sampling order and the output transmission order.The sequencer circuit uses a segmentation method,which adopts intermediate relay registers for the high frequency band and a delay chain circuit for the low frequency band.A self-calibration circuit is designed to track the change of clock skew between the sampling clock and the transmission clock in real time,and to calibrate the sequencer circuit in real time.In addition,the method of latch and key path transformation is designed.On the basis of not affecting the skew between the original sampling clock and the transmission clock,the additional fractional cycle output delay function is implemented in three segments.The sample chip test results of the RCD timing-hold circuit manufactured with TSMC 28 nm process show that the circuit solution can meet the requirements of the first-generation DDR5 RCD memory buffer operating at 4800MT/s data rate.The simulation results of the key circuit show that the circuit solution can further meet the requirements of the second generation DDR5 RCD memory buffer operating at a maximum speed of 6400MT/s.