| Recent years, as the digital signal processing technology developing, processing digital signals after converting analog signals to digital signals has been the mainstream scheme in engineering fields, such as software defined radio and measuring instruments fields. While the frequency of the signal goes high, the difficulty and complexity of the system design is increasing, so is improving the system performance. How to design a full functional and good performance high speed sampling system is of great value in research and application.The theme of this thesis is the key technology of high speed muti-channels sampling system research and implementation. The technique data includes 4 GSPS sampling rate, 8 bit resolution and 8 channels. This thesis relates how to converting the system technique data into each sub-system technique data by means of survey and simulation. Theoretical analysis and Matlab modeling on offset mismatch, gain mismatch and time skew in time interleaved ADC system has been done. Thus the determinants of the amplitude and frequency of spurious signal are maintained. Then the ADC calibration scheme is set out based on the work above. As the same time, the problems of metastable state and muti-pins data unaligned are researched. The path delay of clock and data is analysized. The scheme of inserting FPGA IODelay primitives is presented to adjust the path delay. Data aligned to clock edge algorithm and muti-pins data aligned algorithm are proposed to solve the problems before. The flow and implement in FPGA of the algorithm is also described.At last, the debug process is described in detail. Data aligned to clock edge algorithm and muti-pins data aligned algorithm turn out to be right by functionality. The problems are solved and the ADC data can be transferred correctly. The spectrum of the ADC which has been calibrated is pure. The test technique data of the system is higher than target and the task is fulfilled. |
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