Design And Optimization Of Hierarchical Storage Structure For Heterogeneous Multi-core System

As a combination of multi-core technology and Network-on-Chip technology,the multiple-core system has the inherent characteristic of frequent data interaction between the processor core and the chip.So it is urgent to need the efficient bandwidth of the memory interface to support the parallel transmission of multi-channel data.Traditional simple storage controllers cannot provide an access service for multiple tasks at the same time.Learning from the idea of multi-process time-sharing CPU resource,the thesis uses the bandwidth difference between memory interface and single processor core to redistribute the bandwidth of memory interface,enabling multiple tasks to be shared on the SDRAM side and operated on the user side in parallel.Based on the above research,the thesis designs a hierarchical Memory interface(HMI),simultaneously supporting 6 channel parallel random access,fully releasing the memory bandwidth,and significantly improveing the target system performance.The main work is as follows:1.Firstly,the thesis analyzes the target multi-core system for the design requirements of HMI,and puts forward the design of HMI.The HMI has the flexible method of the data organization and the rich access pattern,and optimizes the user-input way,greatly reducing the user programming difficulty.At the same time,The HMI has the flexible address channel release mechanism,making the tasks switched more efficiently and the instruction words sent more conveniently.2.Secondly,this thesis introduces the overall framework of the above scheme,as well as the circuit structure,function and working principle of each key module.3.Thirdly,in this paper,a common multi-FIFO parallel memory model is abstracted from the practical problem of HMI data channel,and a parallel FIFO solution based on RAM storage array is proposed in view of the low resource utilization,which can be used to ensure the consistent performance.A large amount of dedicated block RAM resources are saved,and resource consumption is predictable,at the expense of adding a relatively small number of common resources.4.Finally,this thesis integrates the HMI design into the target multi-core system,and tests the performance of the HMI design by loading the algorithm tasks of the different ratios of compution-time to access-time(RCA).The experimental results show that,compared with the previous version of Mami,the HMI interface has an average performance increase of 8.97% for the matrix transpose of zero operation requirements,and 43.8% for the tasks of RCA less than 1,and 1 for the task of RCA far greater than 7.6%.In addition,in some applications,its flexible instruction input increases performance by an average of 200%.To sum up,the HMI memory interface designed in the thesis can effectively improves the data transmission parallelism and improves the system performance,achieving the expected target.