Optimization Of Internal Storage Architecture Of Heterogeneous Multi-core SOC Processors

The performance of microprocessors has been greatly improved by the development of heterogeneous multi-core technology,Meanwhile,the bandwidth difference between the processor and the external memory has severely restricted the performance of the processor.For a heterogeneous multi-core So C system in high-density computing,thesis proposes a memory design scheme.The solution increases access bandwidth and reduces the frequency of accessing external memory by reusing some local free memory resources that have been idle for a long time as secondary shared cache.Meanwhile,the distributed cache shared secondary cache combined with the hierarchical memory structure of multiple parallel to reduce the speed difference between system processing data and external memory,improve data access efficiency,and optimize the performance of the system.The main contents of thesis are as follows:1.In view of the memory access characteristics and data memory requirements of heterogeneous multi-core systems,thesis designs a hierarchical memory structure that can reuse local free memory resources as a secondary cache.This architecture addresses the memory resources of functional units that have not been used for a long time in the system,with a shared memory structure in the logical function and a distributed memory structure in the physical structure,and then uses these uniformly addressed memory blocks as a secondary cache for other computing nodes to access data.This distributed cache,centralized control structure greatly saves on-chip memory resources,reduces area,alleviates the mismatch between on-chip and off-chip memory speeds,and improves system access performance.2.Hardware design of the distributed shared cache architecture according to the design plan.The overall hardware architecture of the cache is first described and the main functional modules are divided according to their functions,including the cache control module,the data cache module,the on-chip network communication module and the multiplexed data parallel transfer module.Finally the data channels for these functional modules are described in detail,including the design and implementation of the two main types of data channels and the workflow.3.Integrate the distributed cache architecture onto the target system's heterogeneous multi-core system,build a testbed,load different types of tasks,define performance metrics,verify its functionality and evaluate resource consumption and performance.The final experimental results show that the average performance of the tasks in single mode is improved by 40.6% and the average performance of the tasks in stream mode is improved by 13.3% compared to the structure without cache.In summary,the distributed shared cache structure designed in thesis can effectively improve the system performance.