Design And Implementation Of Data Prefetcher

The fact that modern processors develop rapidly while memory develops slowly causes excessive delays in the memory access process.It seriously affects the operating speed of the processor.Many domestic and foreign researchers have proposed a variety of technical solutions to solve this problem.The application of prefetching technology is one of the key research areas.The use of prefetch technology can put data into the cache in advance,effectively reduce processor access delay,and improve processor performance.Therefore,the research on prefetch technology has important practical significance and application value.The topic of this paper comes from the enterprise BOOM processor research project.The Next Line Prefetch strategy and the Adapt Prefetch mechanism are proposed based on the research of the BOOM processor's non-blocking cache structure.The problems of the traditional sequential prefetching strategy are revealed and then the design is optimized by studying the relationship between the traditional sequential prefetching mechanism and the non-blocking cache structure.Compared with the processor that adopts the traditional sequential prefetching strategy,the performance of optimized design is improved by nearly4%.The Adapt Prefetch mechanism in BOOM processor can dynamically adjust the prefetch degree K.The performance of the processor is improved by nearly 6% compared with the processor based on the traditional sequential prefetch strategy.Both prefetch strategies reduce the first-level cache failure rate to less than 3%.Then,the performance counters to count the number of read and write operations and the number of read and write operations failures in the first-level cache are designed.Based on this result,the influence of the prefetcher on the cache work can be obtained.The experiment uses the standard computer performance test program SPEC CPU2006 to test the processor performance on the Xilinx zc706 FPGA development board.The results show that both prefetchers can be successfully integrated into the BOOM processor to complete the access operation from the first level cache to the second level cache.The performance of the processor has been improved,and has met the design requirements.