A Study On Cache Configuration And Organization In Many-core DSP System

The problem of memory wall is increasingly serious,resulting from the increasingly large performance gap between the processor and off-chip memory and the popular many-core desgin style.In this case,the memory sytem of high speed is the necessary foundation for high performace computing.Cache in many-core systems is significant for enhancing the performance of memory system.In this paper,methods of Cache architecture optimization are studied and a series of experiments based on CACTI and GEM5 are carried out to explore Cache.The research includes Cache configuration,multi-level Cache organization and data prefetching.Specific optimized configurations and orgazitions are proposed.(1)The suitable associativity is 2 for L1 and 8 for L2 respectively.Cacheline size is configured as 32 or 64 Bytes for better performance.(2)When size ratio between L2 and L1 is small,exclusive relationship is friendly to cache performance,while inclusive relationship between L2 and L1 has little effect on cache performance if the ration is greater than 8.(3)For the applications that require frequently data share and exchange,properly distributed and globally shared L2 can supply better performance than the cluster-shared L2.(4)Compared to MESI coherence Protocol,Improved MOESI coherence Protocol supplies no significant improvement in system performance.And according to principles of simplicity and reliability,the MESI coherence protocol is preferred.(5)Compared to stride prefetching,sequential prefetching can offer better performance in terms of digital signal processing.