Optimization Of Secondary Shared Memory In Heterogeneous Multi-core Systems For High-density Computing

As the performance gap between multi-core processors and memory grows larger,the problem of "storage walls" is getting worse.The target system for this thesis originally directly interacts with the main memory SDRAM.Because the main memory SDRAM can provide users with limited memory access and the speed of responding to the memory access task is slow,this thesis proposes a hierarchical secondary shared storage structure.The storage structure supports 14 parallel data channels and random access memory,and uses SRAM as the cache medium.It is dedicated to solving the problem that the system has limited bandwidth and slow response to the memory access task.The main work of the thesis is as follows:1.According to the multi-task parallel memory access requirements proposed by the target system,this thesis proposes a multi-address channel management mechanism.The address channel includes a rich memory access mode and flexible data organization,which greatly improves the system's parallel access efficiency and improves system performance.2.Through the analysis of the target multi-core system,this thesis proposes a hierarchical storage structure that is compatible with the target multi-core system.The structure adopts the group-associated address mapping method,and adopts the cache replacement strategy of counting replacement.At the same time,in the operation gap of the system,the off-chip memory bandwidth is fully utilized for data pre-reading and cached data synchronization operation to improve the cache structure.The hit rate increases the bandwidth of the system's memory on the memory side and improves the performance of the target multi-core system.3.According to the practical problems encountered in designing hierarchical storage structure,this thesis designs a multi-channel FIFO,which saves a lot of storage resources without affecting the hierarchical storage performance.4.This thesis integrates the hierarchical memory into the target system,and tests the performance of the hierarchical memory to improve the system performance by loading the system with different tasks than the memory access.The experimental results show that compared with the previous version of the storage cluster,the shared cache structure has an average performance improvement of 0.5% for matrix transposition tasks with zero computational requirements.For a complex addition task with a computational memory ratio of less than 1,the performance is improved by an average of 29.3.%;For a fast Fourier transform task with a calculated access ratio greater than 1,the performance is increased by an average of 20.6%.In summary,the shared cache structure designed by the thesis can effectively improve the parallelism of data transmission,improve system performance,and achieve the expected goals.