The Design Of Shared L2-Cache Structure Based On Heterogeneous Multicore System

The advent of multicore improves the microprocessor performance significantly, and highlights the speed difference between the processor and memory. The memory becomes the main factors that limit the processor bandwidth. In this thesis, a hierarchical shared secondary storage (L2-Cache) structure for a heterogeneous multicore system, which faces high density calculation, is proposed to ease the speed difference between data processing and data storage. The hierarchical storage structure provides object data caching function and reduces the pollution of secondary storage using count replacement strategy to improve valid data hit rate. The structure can also increase the effective memory bandwidth by L2 - main memory synchronous operation and accurately prefetch in data calculation interval time. Final verification results show that L2-Cache design can adapt for various data features of different applications. The new design increases about 31.1% of the average fetch performance, gains about 1.573 of the highest speed ratio of different sizes of matrix, and reduces about 27.8% of the average computation time.The main work is as follows:1?This thesis analyzes the HMCS multicore system, and then puts forward a kind of cache structure adapted to multicore system, which is called Shared L2-D Cache structure.This structure is optimized in the mapping method of cache, replacement algorithm, data prefetching, prefetching data and operating L2-main memory synchronous operation in the computing interval time to reduce the memory bandwidth in data fetching operation.The shared L2-D Cache structure can improve the system operation performance.2?This thesis introduces the hardware design of shared L2-D Cache structure about the overall architecture and parting modules, then introduces the detail function, working principle, hardware design, and the work flow of key modules. This design mainly includes the control channel and data path. The control channel calculates the read/write address and prefetching address according to control commands and data storage request that are sent by HMCS system, then judges addresses hit or not in order to distinguish different task types, and finally distributes tasks to the data path according to the task priority.3?This thesis intergrates the hardware design into the HMCS multicore system and loads tasks with different ratio between calculation and memory access to verify the function of the design and performance. Finally this thesis discusses the influence of C Cache structure in task execution cycles and the impact of data parallelism.