Research On Key Technologies Of RS-485 Transceiver With Limited Slew Rate

With the progress of science and technology,the communication in daily life become more and more important,due to the character of long transmission distance,fast transmission distance,high applicability the RS-485 standard have a wider market of the industry,agriculture,military and other fields.transceiver in the RS-485standard has a key role in communication,so the research for the RS-485 transceiver is of great significance.In this paper,the key technologies of limited slew rate RS-485 transceivers are studied,according to the principle of RS-485 bus transceiver,whole circuit is divided into two parts of receiver circuit and transmitter circuit,the key technology are(1)hysteresis comparator of the receiving circuit(2)limited slew rate driver circuit(3)±15k V ESD protection for bus pins and±8k V ESD protection for other pins.The receiving circuit also includes an input circuit,an output drive circuit,and the transmitter circuit includes an overtemperature protection circuit and a control circuit.After the detailed design indicators are determined,a RS-485 communication standard based limited slew rate transceiver is designed using Global Foundries 0.18um BCD process.The transistor level circuit structure of each module is designed with Cadence Spectre simulation tool and verified by pre-simulation.Through the simulation results can be obtained,this paper designed transceiver in the whole temperature range(55??125?),the full voltage domain(4.5 V to 5.5 V),the whole process Angle,the receiver circuit differential input threshold voltage between-200 m V?-50 m V,when input ports A,B of receiver circuit for-7 V input voltage,minimum input current of-57.6 u A,when the input voltage is 12 V,the maximum input current 58.5 u A,the minimum input impedance is 134 k.The maximum rise and fall delay is 19.84ns and19.93ns,respectively.The minimum output logic high level is 4.25V,the maximum output logic low level is 175m V,the maximum short-circuit current is 67.6m A,and the maximum output leakage current of high resistance is 3.3n A.The maximum input logic low level of the sending circuit is 0.9V,and the minimum input logic high level is1.9V.In no load and connected 54?or 100?load difference,the minimum of Differential transmitter Output Voltage is 2.25 V,maximum common-mode output voltage is 2.75 V.The maximum short-circuit current of NMOS branch is 222.6m A,and the minimum short-circuit current of PMOS branch is-206m A.The high resistance output leakage current is all below 2u A.At the transmission rate of 20Mbps,the rise and fall delay are 5.56ns?15.3ns and 6.18ns?16.6ns,respectively,the rise and fall time are 1.11ns?2.92ns and 1.08ns?2.39ns,respectively.At the transmission rate of 250kbps with limited slew rate,the rise and fall delay are 480ns-817ns and 480ns-818ns,respectively,and the rise and fall time are 719ns-1027ns and 719ns-1027ns,respectively.The maximum turn-off temperature of the circuit is 188?,and the minimum reset temperature is 144?.In addition,in order to prevent the damage caused by electrostatic discharge to the internal circuit of the chip,this paper designed±8k V ESD protection circuit for the input logic pin,output logic pin and power supply ground,and designed±15k V ESD protection circuit for the bus pin using DDSCR structure.On the basis of meeting the design requirements through the pre-design,the layout design of RS-485 transceiver with limited slew rate is completed with Virtuoso software.The chip area is 2.49mm~2 and has been verified by DRC,LVS and ERC.Combined with the circuit diagram to complete the circuit simulation,and taped out.