Application Of Low Power Technology In Microprocessor Chip Design

With the rapid development of integrated circuits,the requirements for power consumption indicators have become higher and higher.Now it is a design indicator that needs to be considered as important as performance and area.Especially for the microprocessor,because the circuit execution control component and arithmetic logic component of the microprocessor operate frequently,which will cause a large power consumption,how to reduce the power consumption of the microprocessor is also a popular research topic in recent years.This subject mainly studies the application of low power consumption technology in microprocessor design.Low power consumption technology will be involved in all stages of chip design.This topic applies low power consumption technology in the stage of system design and layout implementation.This subject is based on the micro-processing of Y-type DSP to perform various low-power processing.On the microprocessor,the three major parts of the general data logic circuit,memory circuit and clock network will cause a lot of power consumption.To reduce power consumption,the first consideration is to reduce the operating voltage of the microprocessor.This design uses LDO voltage division to reduce the core voltage to reduce power consumption.Then,the low-power management technology of the clock is applied to the design of the system.The low-power module works to control each clock module,and the three low-power modes IDLE mode,STANDBY mode,and HALT mode are designed to turn off the idle clock to reduce power consumption.Finally,a low-power design is performed on the memory in order to make access more efficient and reduce unnecessary access,this design divides the two memory banks of SRAM and ROM into blocks,and the memory is divided into blocks with low power consumption design.Only the blocks that need to be accessed need to be accessed.The blocks that are accessed do not need to be driven,so redundant flips are reduced,thereby reducing power consumption.After the above front-end design is completed,the Y-type DSP is designed for low power consumption,using a standard cell library containing multiple threshold voltage cells,using low threshold voltage cells in the critical path to meet the timing,and non-critical paths using high threshold voltage cells to reduce power consumption.In the layout of the microprocessor layout,try to place the macro unit module on the edge,and the logic unit related to the IO signal should be placed near the IO Pad.In the planning of the power network,the macro unit module adds more power supplies.Due to the clock the turnover rate of the network is relatively high,and a metal layer with a small capacitance is used to lay the clock network line and so on.Through the physical implementation from the front-end design to the backend,a series of low-power consumption technologies are applied to reduce the power consumption of the microprocessor chip in this design by 35% compared with foreign chips of the same type.Finally,further improve the chip's low power consumption,optimize the address reorganization for SRAM and ROM,make the frequently accessed addresses concentrated in a small module,avoid driving large-area memory banks,and achieve the purpose of saving power Through this improvement,the power consumption of this version of Y-type DSP is reduced by 11.3% compared with the previous version.