| The performance of a processor relies on two important resources: the microprocessor's computing ability of processing data and the memory hierarchy that stores data and supports data to the micro-processor. Unfortunately, as technologies scale down, the progress of the memory hierarchy, which uses traditional memory technologies, is slower than that of the micro-processor. Especially, when the micro-processor design moves to the regime of chip-multi-processors (CMPs), the gap between processors and memory hierarchy becomes even larger and thus results in the well known problem of "memory wall".;First, the increasing number of processing cores on a single chip requires more data to be fed in time to support the high computing throughput. It means that more memory needs to be integrated on-chip to maintain the high performance. The low density of the traditional SRAM technology, however, limits the capacity of on-chip memory. Second, since the power consumption issue has become one of the most important design concerns, the high leakage power consumption of traditional SRAM/DRAM technologies significantly impedes the progress of the memory hierarchy. This problem becomes even worse as the technologies scale down and more memory is integrated. Third, the data stored in SRAM/DRAM memory become more and more vulnerable to radiation-based soft errors with technology scaling. The extra overhead of error correction mechanisms further limits the improvement of performance and induces more power consumption. As a summary, traditional memory technologies, such as SRAM and DRAM, cannot satisfy the memory requirement with technology scaling because of low density, high standby power, and poor reliability.;To attack the "memory wall", various non-volatile-memory (NVM) technologies have been proposed as candidates for the design of future memory hierarchy because of their advantages of high density, zero standby power, fast access speed, non-volatility, etc. These memory technologies include Spin Torque Transfer Random-access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random-access Memory (RRAM), etc. With these emerging NVMs, the memory hierarchy design needs to be rethought to achieve high performance, low power consumption, and high reliability. Since these emerging memory technologies have different characters, the following three questions should be answered to achieve the design goals: (1) how to choose the proper memory technologies for different levels of the memory hierarchy? (2) how to improve the architecture of the traditional memory hierarchy to facilitate the adoption of these emerging memories? (3) how to leverage the advantages of different memory technologies?;In this dissertation, we intend to answer these questions by exploring the memory hierarchy design from different angles. First, we propose to replace different levels of a traditional memory hierarchy with proper emerging memory technologies, according to their characters. We will show that both performance and power consumption can be improved after we apply modifications to the memory architectures. At the same time, we find it feasible to leverage advantages from different memory technologies by using the hybrid memory design. Second, we presents a analytical model named "Moguls" to theoretically study the optimization design of a memory hierarchy. With the help of this model, we can not only estimate the level number and the corresponding capacity of the memory hierarchy, but also find out the best choice of memory technology in each level quickly. Third, we explore the vulnerability of the CMPs to radiation-based soft errors by replacing different levels of on-chip memory with STT-RAMs. The results show the trade-off among reliability, performance, and power consumption. |
