Research On Key Techniques Of Low Power Radiation Hardened Flip-flop Design

As transistor sizes scale down,the increasing soft error rate of flip-flops has become an important factor that must be considered in the design of highly reliable integrated circuits.Therefore,the design of harded flip-flops has become a research hotspot.The easiest way to reduce the soft errors of the circuit is to keep the storage node with a sufficient amount of charge,but this is unrealistic in nanotechnology because the circuit node voltage and capacitance are positively related to the size of the transistor.As the size of the transistor enters the nanoscale As a result,the voltage and capacitance of the circuit node will also decrease,which will cause the node charge to be greatly reduced.The other solution is to use the traditional three module redundancy(TMR)technology.Although it is the most effective solution,this technology excessively increases the area,power consumption and delay overhead in the circuit,so the scheme cannot guarantee that the circuit meets the design specifications under any circumstances.Therefore,it is more common now to harden the flip-flop structure directly.In terms of the development of very large scale integrated circuits,the process size is continuously shrinking,and it is developing to nano-devices;the chip area is increasing,so the integration on a chip is increasing;multimedia The development of technology The demand for highperformance chips has increased the clock frequency of the chip,causing the chip's power consumption to increase sharply,which has led to the rapid increase in the cost of packaging and heat sinks,and has reached the limit that the packaging technology can handle,and it is too high.The power consumption has caused great challenges to the endurance of various portable devices.Therefore,the design of low-power ruggedized triggers is an urgent technical need for VLSI designs.This dissertation mainly studies the types and origin of power consumption of CMOS integrated circuits,describes the indicators used to evaluate the performance of flip-flops in integrated circuits,and briefly introduces the basic principles of reducing the power consumption of flip-flops(true single phase Clock technology),its structural advantages and design difficulties.This dissertation proposes a low-power type hardened Flip-flop: TSPC-RHM.The overall idea is to use the RHM unit to tolerate internal node generation of SEU,use a true single-phase clock to reduce the total power consumption of the circuit,and use the C element to shield the internal glitch propagation.To the output,make the output waveform more regular.HSPICE simulation shows that the TSPC-RHM flip-flop achieves a good compromise between delay,power consumption and area overhead.The average delay is reduced by 26.11%,the average power consumption is reduced by 70.82%,the average delay product of power consumption is reduced by 76.78%,and the area is reduced by an average of 28.13%.PVT fluctuation analysis shows that the TSPC-RHM Flip-flop is not sensitive to process fluctuations.This dissertation conducts a comprehensive analysis of eleven types of TMR latches,briefly introduces the constituent modules of three-mode redundant latches,a variety of voter structures and structural sources,and uses HSPICE simulation tools to simulate a variety of triple modular redundant latches.The simulator's simulation waveform,and measure its delay and power consumption.After comprehensive comparison,the overall performance of the TMR7 latch(using the P3 + N1 voting unit)is optimal.